1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
17#include "HexagonRegisterInfo.h"
18#include "MCTargetDesc/HexagonBaseInfo.h"
19#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
20#include "llvm/Target/TargetFrameLowering.h"
21#include "llvm/Target/TargetInstrInfo.h"
22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
28struct EVT;
29
30class HexagonInstrInfo : public HexagonGenInstrInfo {
31  virtual void anchor();
32  const HexagonRegisterInfo RI;
33  const HexagonSubtarget &Subtarget;
34  typedef unsigned Opcode_t;
35
36public:
37  explicit HexagonInstrInfo(HexagonSubtarget &ST);
38
39  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
40  /// such, whenever a client has an instance of instruction info, it should
41  /// always be able to get register info as well (through this method).
42  ///
43  const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
44
45  /// isLoadFromStackSlot - If the specified machine instruction is a direct
46  /// load from a stack slot, return the virtual or physical register number of
47  /// the destination along with the FrameIndex of the loaded stack slot.  If
48  /// not, return 0.  This predicate must return 0 if the instruction has
49  /// any side effects other than loading from the stack slot.
50  unsigned isLoadFromStackSlot(const MachineInstr *MI,
51                               int &FrameIndex) const override;
52
53  /// isStoreToStackSlot - If the specified machine instruction is a direct
54  /// store to a stack slot, return the virtual or physical register number of
55  /// the source reg along with the FrameIndex of the loaded stack slot.  If
56  /// not, return 0.  This predicate must return 0 if the instruction has
57  /// any side effects other than storing to the stack slot.
58  unsigned isStoreToStackSlot(const MachineInstr *MI,
59                              int &FrameIndex) const override;
60
61
62  bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
63                         MachineBasicBlock *&FBB,
64                         SmallVectorImpl<MachineOperand> &Cond,
65                         bool AllowModify) const override;
66
67  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
68
69  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
70                        MachineBasicBlock *FBB,
71                        const SmallVectorImpl<MachineOperand> &Cond,
72                        DebugLoc DL) const override;
73
74  bool analyzeCompare(const MachineInstr *MI,
75                      unsigned &SrcReg, unsigned &SrcReg2,
76                      int &Mask, int &Value) const override;
77
78  void copyPhysReg(MachineBasicBlock &MBB,
79                   MachineBasicBlock::iterator I, DebugLoc DL,
80                   unsigned DestReg, unsigned SrcReg,
81                   bool KillSrc) const override;
82
83  void storeRegToStackSlot(MachineBasicBlock &MBB,
84                           MachineBasicBlock::iterator MBBI,
85                           unsigned SrcReg, bool isKill, int FrameIndex,
86                           const TargetRegisterClass *RC,
87                           const TargetRegisterInfo *TRI) const override;
88
89  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
90                      SmallVectorImpl<MachineOperand> &Addr,
91                      const TargetRegisterClass *RC,
92                      SmallVectorImpl<MachineInstr*> &NewMIs) const;
93
94  void loadRegFromStackSlot(MachineBasicBlock &MBB,
95                            MachineBasicBlock::iterator MBBI,
96                            unsigned DestReg, int FrameIndex,
97                            const TargetRegisterClass *RC,
98                            const TargetRegisterInfo *TRI) const override;
99
100  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
101                       SmallVectorImpl<MachineOperand> &Addr,
102                       const TargetRegisterClass *RC,
103                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
104
105  MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
106                                      MachineInstr* MI,
107                                      const SmallVectorImpl<unsigned> &Ops,
108                                      int FrameIndex) const override;
109
110  MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
111                                      MachineInstr* MI,
112                                      const SmallVectorImpl<unsigned> &Ops,
113                                      MachineInstr* LoadMI) const override {
114    return nullptr;
115  }
116
117  unsigned createVR(MachineFunction* MF, MVT VT) const;
118
119  bool isBranch(const MachineInstr *MI) const;
120  bool isPredicable(MachineInstr *MI) const override;
121  bool PredicateInstruction(MachineInstr *MI,
122                    const SmallVectorImpl<MachineOperand> &Cond) const override;
123
124  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
125                           unsigned ExtraPredCycles,
126                           const BranchProbability &Probability) const override;
127
128  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
129                           unsigned NumTCycles, unsigned ExtraTCycles,
130                           MachineBasicBlock &FMBB,
131                           unsigned NumFCycles, unsigned ExtraFCycles,
132                           const BranchProbability &Probability) const override;
133
134  bool isPredicated(const MachineInstr *MI) const override;
135  bool isPredicated(unsigned Opcode) const;
136  bool isPredicatedTrue(const MachineInstr *MI) const;
137  bool isPredicatedTrue(unsigned Opcode) const;
138  bool isPredicatedNew(const MachineInstr *MI) const;
139  bool isPredicatedNew(unsigned Opcode) const;
140  bool DefinesPredicate(MachineInstr *MI,
141                        std::vector<MachineOperand> &Pred) const override;
142  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
143                   const SmallVectorImpl<MachineOperand> &Pred2) const override;
144
145  bool
146  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
147
148  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
149                           const BranchProbability &Probability) const override;
150
151  DFAPacketizer*
152  CreateTargetScheduleState(const TargetMachine *TM,
153                            const ScheduleDAG *DAG) const override;
154
155  bool isSchedulingBoundary(const MachineInstr *MI,
156                            const MachineBasicBlock *MBB,
157                            const MachineFunction &MF) const override;
158  bool isValidOffset(const int Opcode, const int Offset) const;
159  bool isValidAutoIncImm(const EVT VT, const int Offset) const;
160  bool isMemOp(const MachineInstr *MI) const;
161  bool isSpillPredRegOp(const MachineInstr *MI) const;
162  bool isU6_3Immediate(const int value) const;
163  bool isU6_2Immediate(const int value) const;
164  bool isU6_1Immediate(const int value) const;
165  bool isU6_0Immediate(const int value) const;
166  bool isS4_3Immediate(const int value) const;
167  bool isS4_2Immediate(const int value) const;
168  bool isS4_1Immediate(const int value) const;
169  bool isS4_0Immediate(const int value) const;
170  bool isS12_Immediate(const int value) const;
171  bool isU6_Immediate(const int value) const;
172  bool isS8_Immediate(const int value) const;
173  bool isS6_Immediate(const int value) const;
174
175  bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
176  bool isConditionalTransfer(const MachineInstr* MI) const;
177  bool isConditionalALU32 (const MachineInstr* MI) const;
178  bool isConditionalLoad (const MachineInstr* MI) const;
179  bool isConditionalStore(const MachineInstr* MI) const;
180  bool isNewValueInst(const MachineInstr* MI) const;
181  bool isNewValue(const MachineInstr* MI) const;
182  bool isDotNewInst(const MachineInstr* MI) const;
183  int GetDotOldOp(const int opc) const;
184  int GetDotNewOp(const MachineInstr* MI) const;
185  int GetDotNewPredOp(MachineInstr *MI,
186                      const MachineBranchProbabilityInfo
187                      *MBPI) const;
188  bool mayBeNewStore(const MachineInstr* MI) const;
189  bool isDeallocRet(const MachineInstr *MI) const;
190  unsigned getInvertedPredicatedOpcode(const int Opc) const;
191  bool isExtendable(const MachineInstr* MI) const;
192  bool isExtended(const MachineInstr* MI) const;
193  bool isPostIncrement(const MachineInstr* MI) const;
194  bool isNewValueStore(const MachineInstr* MI) const;
195  bool isNewValueStore(unsigned Opcode) const;
196  bool isNewValueJump(const MachineInstr* MI) const;
197  bool isNewValueJumpCandidate(const MachineInstr *MI) const;
198
199
200  void immediateExtend(MachineInstr *MI) const;
201  bool isConstExtended(MachineInstr *MI) const;
202  int getDotNewPredJumpOp(MachineInstr *MI,
203                      const MachineBranchProbabilityInfo *MBPI) const;
204  unsigned getAddrMode(const MachineInstr* MI) const;
205  bool isOperandExtended(const MachineInstr *MI,
206                         unsigned short OperandNum) const;
207  unsigned short getCExtOpNum(const MachineInstr *MI) const;
208  int getMinValue(const MachineInstr *MI) const;
209  int getMaxValue(const MachineInstr *MI) const;
210  bool NonExtEquivalentExists (const MachineInstr *MI) const;
211  short getNonExtOpcode(const MachineInstr *MI) const;
212  bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
213  bool PredOpcodeHasNot(Opcode_t Opcode) const;
214
215private:
216  int getMatchingCondBranchOpcode(int Opc, bool sense) const;
217
218};
219
220}
221
222#endif
223