HexagonMachineFunctionInfo.h revision b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 
1//=- HexagonMachineFuctionInfo.h - Hexagon machine function info --*- C++ -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef HexagonMACHINEFUNCTIONINFO_H
11#define HexagonMACHINEFUNCTIONINFO_H
12
13#include "llvm/CodeGen/MachineFunction.h"
14
15namespace llvm {
16
17  namespace Hexagon {
18    const unsigned int StartPacket = 0x1;
19    const unsigned int EndPacket = 0x2;
20  }
21
22
23/// Hexagon target-specific information for each MachineFunction.
24class HexagonMachineFunctionInfo : public MachineFunctionInfo {
25  // SRetReturnReg - Some subtargets require that sret lowering includes
26  // returning the value of the returned struct in a register. This field
27  // holds the virtual register into which the sret argument is passed.
28  unsigned SRetReturnReg;
29  std::vector<MachineInstr*> AllocaAdjustInsts;
30  int VarArgsFrameIndex;
31  bool HasClobberLR;
32  bool HasEHReturn;
33
34  std::map<const MachineInstr*, unsigned> PacketInfo;
35
36
37public:
38  HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0),
39    HasEHReturn(false) {}
40
41  HexagonMachineFunctionInfo(MachineFunction &MF) : SRetReturnReg(0),
42                                                    HasClobberLR(0),
43                                                    HasEHReturn(false) {}
44
45  unsigned getSRetReturnReg() const { return SRetReturnReg; }
46  void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
47
48  void addAllocaAdjustInst(MachineInstr* MI) {
49    AllocaAdjustInsts.push_back(MI);
50  }
51  const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
52    return AllocaAdjustInsts;
53  }
54
55  void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
56  int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
57
58  void setStartPacket(MachineInstr* MI) {
59    PacketInfo[MI] |= Hexagon::StartPacket;
60  }
61  void setEndPacket(MachineInstr* MI)   {
62    PacketInfo[MI] |= Hexagon::EndPacket;
63  }
64  bool isStartPacket(const MachineInstr* MI) const {
65    return (PacketInfo.count(MI) &&
66            (PacketInfo.find(MI)->second & Hexagon::StartPacket));
67  }
68  bool isEndPacket(const MachineInstr* MI) const {
69    return (PacketInfo.count(MI) &&
70            (PacketInfo.find(MI)->second & Hexagon::EndPacket));
71  }
72  void setHasClobberLR(bool v) { HasClobberLR = v;  }
73  bool hasClobberLR() const { return HasClobberLR; }
74
75  bool hasEHReturn() const { return HasEHReturn; };
76  void setHasEHReturn(bool H = true) { HasEHReturn = H; };
77};
78} // End llvm namespace
79
80#endif
81