HexagonRegisterInfo.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef HexagonREGISTERINFO_H
16#define HexagonREGISTERINFO_H
17
18#include "llvm/MC/MachineLocation.h"
19#include "llvm/Target/TargetRegisterInfo.h"
20
21#define GET_REGINFO_HEADER
22#include "HexagonGenRegisterInfo.inc"
23
24//
25//  We try not to hard code the reserved registers in our code,
26//  so the following two macros were defined. However, there
27//  are still a few places that R11 and R10 are hard wired.
28//  See below. If, in the future, we decided to change the reserved
29//  register. Don't forget changing the following places.
30//
31//  1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
32//  2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
33//  3. the definition of "IntRegs" in HexagonRegisterInfo.td
34//  4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
35//
36#define HEXAGON_RESERVED_REG_1 Hexagon::R10
37#define HEXAGON_RESERVED_REG_2 Hexagon::R11
38
39namespace llvm {
40
41class HexagonSubtarget;
42class HexagonInstrInfo;
43class Type;
44
45struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
46  HexagonSubtarget &Subtarget;
47
48  HexagonRegisterInfo(HexagonSubtarget &st);
49
50  /// Code Generation virtual methods...
51  const MCPhysReg *
52  getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
53
54  const TargetRegisterClass* const*
55  getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const;
56
57  BitVector getReservedRegs(const MachineFunction &MF) const override;
58
59  void eliminateFrameIndex(MachineBasicBlock::iterator II,
60                           int SPAdj, unsigned FIOperandNum,
61                           RegScavenger *RS = nullptr) const override;
62
63  /// determineFrameLayout - Determine the size of the frame and maximum call
64  /// frame size.
65  void determineFrameLayout(MachineFunction &MF) const;
66
67  /// requiresRegisterScavenging - returns true since we may need scavenging for
68  /// a temporary register when generating hardware loop instructions.
69  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
70    return true;
71  }
72
73  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
74    return true;
75  }
76
77  // Debug information queries.
78  unsigned getRARegister() const;
79  unsigned getFrameRegister(const MachineFunction &MF) const override;
80  unsigned getFrameRegister() const;
81  unsigned getStackRegister() const;
82};
83
84} // end namespace llvm
85
86#endif
87