1//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the Hexagon specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonSubtarget.h"
15#include "Hexagon.h"
16#include "HexagonRegisterInfo.h"
17#include "llvm/Support/CommandLine.h"
18#include "llvm/Support/ErrorHandling.h"
19using namespace llvm;
20
21#define DEBUG_TYPE "hexagon-subtarget"
22
23#define GET_SUBTARGETINFO_CTOR
24#define GET_SUBTARGETINFO_TARGET_DESC
25#include "HexagonGenSubtargetInfo.inc"
26
27static cl::opt<bool>
28EnableV3("enable-hexagon-v3", cl::Hidden,
29         cl::desc("Enable Hexagon V3 instructions."));
30
31static cl::opt<bool>
32EnableMemOps(
33    "enable-hexagon-memops",
34    cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true),
35    cl::desc(
36      "Generate V4 MEMOP in code generation for Hexagon target"));
37
38static cl::opt<bool>
39DisableMemOps(
40    "disable-hexagon-memops",
41    cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false),
42    cl::desc(
43      "Do not generate V4 MEMOP in code generation for Hexagon target"));
44
45static cl::opt<bool>
46EnableIEEERndNear(
47    "enable-hexagon-ieee-rnd-near",
48    cl::Hidden, cl::ZeroOrMore, cl::init(false),
49    cl::desc("Generate non-chopped conversion from fp to int."));
50
51HexagonSubtarget &
52HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
53  // If the programmer has not specified a Hexagon version, default to -mv4.
54  if (CPUString.empty())
55    CPUString = "hexagonv4";
56
57  if (CPUString == "hexagonv2") {
58    HexagonArchVersion = V2;
59  } else if (CPUString == "hexagonv3") {
60    EnableV3 = true;
61    HexagonArchVersion = V3;
62  } else if (CPUString == "hexagonv4") {
63    HexagonArchVersion = V4;
64  } else if (CPUString == "hexagonv5") {
65    HexagonArchVersion = V5;
66  } else {
67    llvm_unreachable("Unrecognized Hexagon processor version");
68  }
69
70  ParseSubtargetFeatures(CPUString, FS);
71  return *this;
72}
73
74HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
75                                   const TargetMachine &TM)
76    : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()),
77      DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32"),
78      InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
79      TSInfo(DL), FrameLowering() {
80
81  // Initialize scheduling itinerary for the specified CPU.
82  InstrItins = getInstrItineraryForCPU(CPUString);
83
84  // UseMemOps on by default unless disabled explicitly
85  if (DisableMemOps)
86    UseMemOps = false;
87  else if (EnableMemOps)
88    UseMemOps = true;
89  else
90    UseMemOps = false;
91
92  if (EnableIEEERndNear)
93    ModeIEEERndNear = true;
94  else
95    ModeIEEERndNear = false;
96}
97
98// Pin the vtable to this file.
99void HexagonSubtarget::anchor() {}
100