HexagonTargetMachine.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implements the info about Hexagon target spec.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonTargetMachine.h"
15#include "Hexagon.h"
16#include "HexagonISelLowering.h"
17#include "HexagonMachineScheduler.h"
18#include "HexagonTargetObjectFile.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/IR/Module.h"
21#include "llvm/PassManager.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Support/TargetRegistry.h"
24#include "llvm/Transforms/IPO/PassManagerBuilder.h"
25#include "llvm/Transforms/Scalar.h"
26
27using namespace llvm;
28
29static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30      cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
31
32static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
33      cl::Hidden, cl::ZeroOrMore, cl::init(false),
34      cl::desc("Disable Hexagon MI Scheduling"));
35
36static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
37      cl::Hidden, cl::ZeroOrMore, cl::init(false),
38      cl::desc("Disable Hexagon CFG Optimization"));
39
40
41/// HexagonTargetMachineModule - Note that this is used on hosts that
42/// cannot link in a library unless there are references into the
43/// library.  In particular, it seems that it is not possible to get
44/// things to work on Win32 without this.  Though it is unused, do not
45/// remove it.
46extern "C" int HexagonTargetMachineModule;
47int HexagonTargetMachineModule = 0;
48
49extern "C" void LLVMInitializeHexagonTarget() {
50  // Register the target.
51  RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
52}
53
54static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
55  return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler());
56}
57
58static MachineSchedRegistry
59SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
60                    createVLIWMachineSched);
61
62/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
63///
64
65/// Hexagon_TODO: Do I need an aggregate alignment?
66///
67HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
68                                           StringRef CPU, StringRef FS,
69                                           const TargetOptions &Options,
70                                           Reloc::Model RM,
71                                           CodeModel::Model CM,
72                                           CodeGenOpt::Level OL)
73  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
74    DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32") ,
75    Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
76    TSInfo(*this),
77    FrameLowering(Subtarget),
78    InstrItins(&Subtarget.getInstrItineraryData()) {
79    initAsmInfo();
80}
81
82// addPassesForOptimizations - Allow the backend (target) to add Target
83// Independent Optimization passes to the Pass Manager.
84bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
85  if (getOptLevel() != CodeGenOpt::None) {
86    PM.add(createConstantPropagationPass());
87    PM.add(createLoopSimplifyPass());
88    PM.add(createDeadCodeEliminationPass());
89    PM.add(createConstantPropagationPass());
90    PM.add(createLoopUnrollPass());
91    PM.add(createLoopStrengthReducePass());
92  }
93  return true;
94}
95
96namespace {
97/// Hexagon Code Generator Pass Configuration Options.
98class HexagonPassConfig : public TargetPassConfig {
99public:
100  HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
101    : TargetPassConfig(TM, PM) {
102    // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
103    // HexagonSubtarget::enableMachineScheduler() { return true; }.
104    // That will bypass the SelectionDAG VLIW scheduler, which is probably just
105    // hurting compile time and will be removed eventually anyway.
106    if (DisableHexagonMISched)
107      disablePass(&MachineSchedulerID);
108    else
109      enablePass(&MachineSchedulerID);
110  }
111
112  HexagonTargetMachine &getHexagonTargetMachine() const {
113    return getTM<HexagonTargetMachine>();
114  }
115
116  virtual ScheduleDAGInstrs *
117  createMachineScheduler(MachineSchedContext *C) const {
118    return createVLIWMachineSched(C);
119  }
120
121  virtual bool addInstSelector();
122  virtual bool addPreRegAlloc();
123  virtual bool addPostRegAlloc();
124  virtual bool addPreSched2();
125  virtual bool addPreEmitPass();
126};
127} // namespace
128
129TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
130  return new HexagonPassConfig(this, PM);
131}
132
133bool HexagonPassConfig::addInstSelector() {
134  HexagonTargetMachine &TM = getHexagonTargetMachine();
135  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
136
137  if (!NoOpt)
138    addPass(createHexagonRemoveExtendArgs(TM));
139
140  addPass(createHexagonISelDag(TM, getOptLevel()));
141
142  if (!NoOpt) {
143    addPass(createHexagonPeephole());
144    printAndVerify("After hexagon peephole pass");
145  }
146
147  return false;
148}
149
150bool HexagonPassConfig::addPreRegAlloc() {
151  if (getOptLevel() != CodeGenOpt::None)
152    if (!DisableHardwareLoops)
153      addPass(createHexagonHardwareLoops());
154  return false;
155}
156
157bool HexagonPassConfig::addPostRegAlloc() {
158  const HexagonTargetMachine &TM = getHexagonTargetMachine();
159  if (getOptLevel() != CodeGenOpt::None)
160    if (!DisableHexagonCFGOpt)
161      addPass(createHexagonCFGOptimizer(TM));
162  return false;
163}
164
165bool HexagonPassConfig::addPreSched2() {
166  const HexagonTargetMachine &TM = getHexagonTargetMachine();
167  const HexagonTargetObjectFile &TLOF =
168    (const HexagonTargetObjectFile &)getTargetLowering()->getObjFileLowering();
169
170  addPass(createHexagonCopyToCombine());
171  if (getOptLevel() != CodeGenOpt::None)
172    addPass(&IfConverterID);
173  if (!TLOF.IsSmallDataEnabled()) {
174    addPass(createHexagonSplitConst32AndConst64(TM));
175    printAndVerify("After hexagon split const32/64 pass");
176  }
177  return true;
178}
179
180bool HexagonPassConfig::addPreEmitPass() {
181  const HexagonTargetMachine &TM = getHexagonTargetMachine();
182  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
183
184  if (!NoOpt)
185    addPass(createHexagonNewValueJump());
186
187  // Expand Spill code for predicate registers.
188  addPass(createHexagonExpandPredSpillCode(TM));
189
190  // Split up TFRcondsets into conditional transfers.
191  addPass(createHexagonSplitTFRCondSets(TM));
192
193  // Create Packets.
194  if (!NoOpt) {
195    if (!DisableHardwareLoops)
196      addPass(createHexagonFixupHwLoops());
197    addPass(createHexagonPacketizer());
198  }
199
200  return false;
201}
202