HexagonBaseInfo.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains small standalone helper functions and enum definitions for
11// the Hexagon target useful for the compiler back-end and the MC libraries.
12// As such, it deliberately does not include references to LLVM core
13// code gen types, passes, etc..
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef HEXAGONBASEINFO_H
18#define HEXAGONBASEINFO_H
19
20#include "HexagonMCTargetDesc.h"
21#include "llvm/Support/ErrorHandling.h"
22
23namespace llvm {
24
25/// HexagonII - This namespace holds all of the target specific flags that
26/// instruction info tracks.
27///
28namespace HexagonII {
29  // *** The code below must match HexagonInstrFormat*.td *** //
30
31  // Insn types.
32  // *** Must match HexagonInstrFormat*.td ***
33  enum Type {
34    TypePSEUDO  = 0,
35    TypeALU32   = 1,
36    TypeCR      = 2,
37    TypeJR      = 3,
38    TypeJ       = 4,
39    TypeLD      = 5,
40    TypeST      = 6,
41    TypeSYSTEM  = 7,
42    TypeXTYPE   = 8,
43    TypeMEMOP   = 9,
44    TypeNV      = 10,
45    TypePREFIX  = 30, // Such as extenders.
46    TypeENDLOOP = 31  // Such as end of a HW loop.
47  };
48
49  enum SubTarget {
50    HasV2SubT     = 0xf,
51    HasV2SubTOnly = 0x1,
52    NoV2SubT      = 0x0,
53    HasV3SubT     = 0xe,
54    HasV3SubTOnly = 0x2,
55    NoV3SubT      = 0x1,
56    HasV4SubT     = 0xc,
57    NoV4SubT      = 0x3,
58    HasV5SubT     = 0x8,
59    NoV5SubT      = 0x7
60  };
61
62  enum AddrMode {
63    NoAddrMode     = 0,  // No addressing mode
64    Absolute       = 1,  // Absolute addressing mode
65    AbsoluteSet    = 2,  // Absolute set addressing mode
66    BaseImmOffset  = 3,  // Indirect with offset
67    BaseLongOffset = 4,  // Indirect with long offset
68    BaseRegOffset  = 5,  // Indirect with register offset
69    PostInc        = 6   // Post increment addressing mode
70  };
71
72  enum MemAccessSize {
73    NoMemAccess = 0,            // Not a memory acces instruction.
74    ByteAccess = 1,             // Byte access instruction (memb).
75    HalfWordAccess = 2,         // Half word access instruction (memh).
76    WordAccess = 3,             // Word access instruction (memw).
77    DoubleWordAccess = 4        // Double word access instruction (memd)
78  };
79
80  // MCInstrDesc TSFlags
81  // *** Must match HexagonInstrFormat*.td ***
82  enum {
83    // This 5-bit field describes the insn type.
84    TypePos  = 0,
85    TypeMask = 0x1f,
86
87    // Solo instructions.
88    SoloPos  = 5,
89    SoloMask = 0x1,
90    // Packed only with A or X-type instructions.
91    SoloAXPos  = 6,
92    SoloAXMask = 0x1,
93    // Only A-type instruction in first slot or nothing.
94    SoloAin1Pos  = 7,
95    SoloAin1Mask = 0x1,
96
97    // Predicated instructions.
98    PredicatedPos  = 8,
99    PredicatedMask = 0x1,
100    PredicatedFalsePos  = 9,
101    PredicatedFalseMask = 0x1,
102    PredicatedNewPos  = 10,
103    PredicatedNewMask = 0x1,
104    PredicateLatePos  = 11,
105    PredicateLateMask = 0x1,
106
107    // New-Value consumer instructions.
108    NewValuePos  = 12,
109    NewValueMask = 0x1,
110    // New-Value producer instructions.
111    hasNewValuePos  = 13,
112    hasNewValueMask = 0x1,
113    // Which operand consumes or produces a new value.
114    NewValueOpPos  = 14,
115    NewValueOpMask = 0x7,
116    // Stores that can become new-value stores.
117    mayNVStorePos  = 17,
118    mayNVStoreMask = 0x1,
119    // New-value store instructions.
120    NVStorePos  = 18,
121    NVStoreMask = 0x1,
122    // Loads that can become current-value loads.
123    mayCVLoadPos  = 19,
124    mayCVLoadMask = 0x1,
125    // Current-value load instructions.
126    CVLoadPos  = 20,
127    CVLoadMask = 0x1,
128
129    // Extendable insns.
130    ExtendablePos  = 21,
131    ExtendableMask = 0x1,
132    // Insns must be extended.
133    ExtendedPos  = 22,
134    ExtendedMask = 0x1,
135    // Which operand may be extended.
136    ExtendableOpPos  = 23,
137    ExtendableOpMask = 0x7,
138    // Signed or unsigned range.
139    ExtentSignedPos  = 26,
140    ExtentSignedMask = 0x1,
141    // Number of bits of range before extending operand.
142    ExtentBitsPos  = 27,
143    ExtentBitsMask = 0x1f,
144    // Alignment power-of-two before extending operand.
145    ExtentAlignPos  = 32,
146    ExtentAlignMask = 0x3,
147
148    // Valid subtargets
149    validSubTargetPos  = 34,
150    validSubTargetMask = 0xf,
151
152    // Addressing mode for load/store instructions.
153    AddrModePos  = 40,
154    AddrModeMask = 0x7,
155    // Access size for load/store instructions.
156    MemAccessSizePos = 43,
157    MemAccesSizeMask = 0x7,
158
159    // Branch predicted taken.
160    TakenPos = 47,
161    TakenMask = 0x1,
162
163    // Floating-point instructions.
164    FPPos  = 48,
165    FPMask = 0x1
166  };
167
168  // *** The code above must match HexagonInstrFormat*.td *** //
169
170  // Hexagon specific MO operand flag mask.
171  enum HexagonMOTargetFlagVal {
172    //===------------------------------------------------------------------===//
173    // Hexagon Specific MachineOperand flags.
174    MO_NO_FLAG,
175
176    HMOTF_ConstExtended = 1,
177
178    /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
179    /// Used for computing a global address for PIC compilations
180    MO_PCREL,
181
182    /// MO_GOT - Indicates a GOT-relative relocation
183    MO_GOT,
184
185    // Low or high part of a symbol.
186    MO_LO16, MO_HI16,
187
188    // Offset from the base of the SDA.
189    MO_GPREL
190  };
191
192} // End namespace HexagonII.
193
194} // End namespace llvm.
195
196#endif
197