MSP430ISelLowering.cpp revision 0c439eb2c8397996cbccaf2798e598052d9982c8 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Target/TargetLoweringObjectFile.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  // Even if we have only 1 bit shift here, we can perform
81  // shifts of the whole bitwidth 1 bit per step.
82  setShiftAmountType(MVT::i8);
83
84  setStackPointerRegisterToSaveRestore(MSP430::SPW);
85  setBooleanContents(ZeroOrOneBooleanContent);
86  setSchedulingPreference(SchedulingForLatency);
87
88  // We have post-incremented loads / stores.
89  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
91
92  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
93  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
94  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
95  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
96  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
97
98  // We don't have any truncstores
99  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
100
101  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
102  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
103  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
104  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
105  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
106  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
107  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
108  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
109  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
110  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
111  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
112  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
113  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
114  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
115  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
116  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
117  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
118  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
119  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
120  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
121  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
122  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
123  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
124  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
125  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
127
128  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
129  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
130  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
131  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
132  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
133  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
134
135  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
140  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
141
142  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
143
144  // FIXME: Implement efficiently multiplication by a constant
145  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
146  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
147  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
148  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
149  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
150  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
151  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
152  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
153  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
154  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
155
156  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
157  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
158  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
159  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
160  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
161  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
162  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
163  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
164  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
165  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
166  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
167  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
168
169  // Libcalls names.
170  if (HWMultMode == HWMultIntr) {
171    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
172    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173  } else if (HWMultMode == HWMultNoIntr) {
174    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
175    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
176  }
177}
178
179SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
180  switch (Op.getOpcode()) {
181  case ISD::SHL: // FALLTHROUGH
182  case ISD::SRL:
183  case ISD::SRA:              return LowerShifts(Op, DAG);
184  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
185  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
186  case ISD::SETCC:            return LowerSETCC(Op, DAG);
187  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
188  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
189  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
190  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
191  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
192  default:
193    llvm_unreachable("unimplemented operand");
194    return SDValue();
195  }
196}
197
198/// getFunctionAlignment - Return the Log2 alignment of this function.
199unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
200  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
201}
202
203//===----------------------------------------------------------------------===//
204//                       MSP430 Inline Assembly Support
205//===----------------------------------------------------------------------===//
206
207/// getConstraintType - Given a constraint letter, return the type of
208/// constraint it is for this target.
209TargetLowering::ConstraintType
210MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
211  if (Constraint.size() == 1) {
212    switch (Constraint[0]) {
213    case 'r':
214      return C_RegisterClass;
215    default:
216      break;
217    }
218  }
219  return TargetLowering::getConstraintType(Constraint);
220}
221
222std::pair<unsigned, const TargetRegisterClass*>
223MSP430TargetLowering::
224getRegForInlineAsmConstraint(const std::string &Constraint,
225                             EVT VT) const {
226  if (Constraint.size() == 1) {
227    // GCC Constraint Letters
228    switch (Constraint[0]) {
229    default: break;
230    case 'r':   // GENERAL_REGS
231      if (VT == MVT::i8)
232        return std::make_pair(0U, MSP430::GR8RegisterClass);
233
234      return std::make_pair(0U, MSP430::GR16RegisterClass);
235    }
236  }
237
238  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
239}
240
241//===----------------------------------------------------------------------===//
242//                      Calling Convention Implementation
243//===----------------------------------------------------------------------===//
244
245#include "MSP430GenCallingConv.inc"
246
247SDValue
248MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
249                                           CallingConv::ID CallConv,
250                                           bool isVarArg,
251                                           const SmallVectorImpl<ISD::InputArg>
252                                             &Ins,
253                                           DebugLoc dl,
254                                           SelectionDAG &DAG,
255                                           SmallVectorImpl<SDValue> &InVals) {
256
257  switch (CallConv) {
258  default:
259    llvm_unreachable("Unsupported calling convention");
260  case CallingConv::C:
261  case CallingConv::Fast:
262    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
263  case CallingConv::MSP430_INTR:
264   if (Ins.empty())
265     return Chain;
266   else {
267    llvm_report_error("ISRs cannot have arguments");
268    return SDValue();
269   }
270  }
271}
272
273SDValue
274MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
275                                CallingConv::ID CallConv, bool isVarArg,
276                                bool &isTailCall,
277                                const SmallVectorImpl<ISD::OutputArg> &Outs,
278                                const SmallVectorImpl<ISD::InputArg> &Ins,
279                                DebugLoc dl, SelectionDAG &DAG,
280                                SmallVectorImpl<SDValue> &InVals) {
281  // MSP430 target does not yet support tail call optimization.
282  isTailCall = false;
283
284  switch (CallConv) {
285  default:
286    llvm_unreachable("Unsupported calling convention");
287  case CallingConv::Fast:
288  case CallingConv::C:
289    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
290                          Outs, Ins, dl, DAG, InVals);
291  case CallingConv::MSP430_INTR:
292    llvm_report_error("ISRs cannot be called directly");
293    return SDValue();
294  }
295}
296
297/// LowerCCCArguments - transform physical registers into virtual registers and
298/// generate load operations for arguments places on the stack.
299// FIXME: struct return stuff
300// FIXME: varargs
301SDValue
302MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
303                                        CallingConv::ID CallConv,
304                                        bool isVarArg,
305                                        const SmallVectorImpl<ISD::InputArg>
306                                          &Ins,
307                                        DebugLoc dl,
308                                        SelectionDAG &DAG,
309                                        SmallVectorImpl<SDValue> &InVals) {
310  MachineFunction &MF = DAG.getMachineFunction();
311  MachineFrameInfo *MFI = MF.getFrameInfo();
312  MachineRegisterInfo &RegInfo = MF.getRegInfo();
313
314  // Assign locations to all of the incoming arguments.
315  SmallVector<CCValAssign, 16> ArgLocs;
316  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
317                 ArgLocs, *DAG.getContext());
318  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
319
320  assert(!isVarArg && "Varargs not supported yet");
321
322  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
323    CCValAssign &VA = ArgLocs[i];
324    if (VA.isRegLoc()) {
325      // Arguments passed in registers
326      EVT RegVT = VA.getLocVT();
327      switch (RegVT.getSimpleVT().SimpleTy) {
328      default:
329        {
330#ifndef NDEBUG
331          errs() << "LowerFormalArguments Unhandled argument type: "
332               << RegVT.getSimpleVT().SimpleTy << "\n";
333#endif
334          llvm_unreachable(0);
335        }
336      case MVT::i16:
337        unsigned VReg =
338          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
339        RegInfo.addLiveIn(VA.getLocReg(), VReg);
340        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
341
342        // If this is an 8-bit value, it is really passed promoted to 16
343        // bits. Insert an assert[sz]ext to capture this, then truncate to the
344        // right size.
345        if (VA.getLocInfo() == CCValAssign::SExt)
346          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
347                                 DAG.getValueType(VA.getValVT()));
348        else if (VA.getLocInfo() == CCValAssign::ZExt)
349          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
350                                 DAG.getValueType(VA.getValVT()));
351
352        if (VA.getLocInfo() != CCValAssign::Full)
353          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
354
355        InVals.push_back(ArgValue);
356      }
357    } else {
358      // Sanity check
359      assert(VA.isMemLoc());
360      // Load the argument to a virtual register
361      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
362      if (ObjSize > 2) {
363        errs() << "LowerFormalArguments Unhandled argument type: "
364             << VA.getLocVT().getSimpleVT().SimpleTy
365             << "\n";
366      }
367      // Create the frame index object for this incoming parameter...
368      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
369
370      // Create the SelectionDAG nodes corresponding to a load
371      //from this parameter
372      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
373      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
374                                   PseudoSourceValue::getFixedStack(FI), 0));
375    }
376  }
377
378  return Chain;
379}
380
381SDValue
382MSP430TargetLowering::LowerReturn(SDValue Chain,
383                                  CallingConv::ID CallConv, bool isVarArg,
384                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
385                                  DebugLoc dl, SelectionDAG &DAG) {
386
387  // CCValAssign - represent the assignment of the return value to a location
388  SmallVector<CCValAssign, 16> RVLocs;
389
390  // ISRs cannot return any value.
391  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
392    llvm_report_error("ISRs cannot return any value");
393    return SDValue();
394  }
395
396  // CCState - Info about the registers and stack slot.
397  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
398                 RVLocs, *DAG.getContext());
399
400  // Analize return values.
401  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
402
403  // If this is the first return lowered for this function, add the regs to the
404  // liveout set for the function.
405  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
406    for (unsigned i = 0; i != RVLocs.size(); ++i)
407      if (RVLocs[i].isRegLoc())
408        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
409  }
410
411  SDValue Flag;
412
413  // Copy the result values into the output registers.
414  for (unsigned i = 0; i != RVLocs.size(); ++i) {
415    CCValAssign &VA = RVLocs[i];
416    assert(VA.isRegLoc() && "Can only return in registers!");
417
418    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
419                             Outs[i].Val, Flag);
420
421    // Guarantee that all emitted copies are stuck together,
422    // avoiding something bad.
423    Flag = Chain.getValue(1);
424  }
425
426  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
427                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
428
429  if (Flag.getNode())
430    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
431
432  // Return Void
433  return DAG.getNode(Opc, dl, MVT::Other, Chain);
434}
435
436/// LowerCCCCallTo - functions arguments are copied from virtual regs to
437/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
438/// TODO: sret.
439SDValue
440MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
441                                     CallingConv::ID CallConv, bool isVarArg,
442                                     bool isTailCall,
443                                     const SmallVectorImpl<ISD::OutputArg>
444                                       &Outs,
445                                     const SmallVectorImpl<ISD::InputArg> &Ins,
446                                     DebugLoc dl, SelectionDAG &DAG,
447                                     SmallVectorImpl<SDValue> &InVals) {
448  // Analyze operands of the call, assigning locations to each operand.
449  SmallVector<CCValAssign, 16> ArgLocs;
450  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
451                 ArgLocs, *DAG.getContext());
452
453  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
454
455  // Get a count of how many bytes are to be pushed on the stack.
456  unsigned NumBytes = CCInfo.getNextStackOffset();
457
458  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
459                                                      getPointerTy(), true));
460
461  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
462  SmallVector<SDValue, 12> MemOpChains;
463  SDValue StackPtr;
464
465  // Walk the register/memloc assignments, inserting copies/loads.
466  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
467    CCValAssign &VA = ArgLocs[i];
468
469    SDValue Arg = Outs[i].Val;
470
471    // Promote the value if needed.
472    switch (VA.getLocInfo()) {
473      default: llvm_unreachable("Unknown loc info!");
474      case CCValAssign::Full: break;
475      case CCValAssign::SExt:
476        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
477        break;
478      case CCValAssign::ZExt:
479        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
480        break;
481      case CCValAssign::AExt:
482        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
483        break;
484    }
485
486    // Arguments that can be passed on register must be kept at RegsToPass
487    // vector
488    if (VA.isRegLoc()) {
489      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
490    } else {
491      assert(VA.isMemLoc());
492
493      if (StackPtr.getNode() == 0)
494        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
495
496      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
497                                   StackPtr,
498                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
499
500
501      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
502                                         PseudoSourceValue::getStack(),
503                                         VA.getLocMemOffset()));
504    }
505  }
506
507  // Transform all store nodes into one single node because all store nodes are
508  // independent of each other.
509  if (!MemOpChains.empty())
510    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
511                        &MemOpChains[0], MemOpChains.size());
512
513  // Build a sequence of copy-to-reg nodes chained together with token chain and
514  // flag operands which copy the outgoing args into registers.  The InFlag in
515  // necessary since all emited instructions must be stuck together.
516  SDValue InFlag;
517  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
518    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
519                             RegsToPass[i].second, InFlag);
520    InFlag = Chain.getValue(1);
521  }
522
523  // If the callee is a GlobalAddress node (quite common, every direct call is)
524  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
525  // Likewise ExternalSymbol -> TargetExternalSymbol.
526  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
527    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
528  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
529    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
530
531  // Returns a chain & a flag for retval copy to use.
532  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
533  SmallVector<SDValue, 8> Ops;
534  Ops.push_back(Chain);
535  Ops.push_back(Callee);
536
537  // Add argument registers to the end of the list so that they are
538  // known live into the call.
539  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
540    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
541                                  RegsToPass[i].second.getValueType()));
542
543  if (InFlag.getNode())
544    Ops.push_back(InFlag);
545
546  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
547  InFlag = Chain.getValue(1);
548
549  // Create the CALLSEQ_END node.
550  Chain = DAG.getCALLSEQ_END(Chain,
551                             DAG.getConstant(NumBytes, getPointerTy(), true),
552                             DAG.getConstant(0, getPointerTy(), true),
553                             InFlag);
554  InFlag = Chain.getValue(1);
555
556  // Handle result values, copying them out of physregs into vregs that we
557  // return.
558  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
559                         DAG, InVals);
560}
561
562/// LowerCallResult - Lower the result values of a call into the
563/// appropriate copies out of appropriate physical registers.
564///
565SDValue
566MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
567                                      CallingConv::ID CallConv, bool isVarArg,
568                                      const SmallVectorImpl<ISD::InputArg> &Ins,
569                                      DebugLoc dl, SelectionDAG &DAG,
570                                      SmallVectorImpl<SDValue> &InVals) {
571
572  // Assign locations to each value returned by this call.
573  SmallVector<CCValAssign, 16> RVLocs;
574  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
575                 RVLocs, *DAG.getContext());
576
577  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
578
579  // Copy all of the result registers out of their specified physreg.
580  for (unsigned i = 0; i != RVLocs.size(); ++i) {
581    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
582                               RVLocs[i].getValVT(), InFlag).getValue(1);
583    InFlag = Chain.getValue(2);
584    InVals.push_back(Chain.getValue(0));
585  }
586
587  return Chain;
588}
589
590SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
591                                          SelectionDAG &DAG) {
592  unsigned Opc = Op.getOpcode();
593  SDNode* N = Op.getNode();
594  EVT VT = Op.getValueType();
595  DebugLoc dl = N->getDebugLoc();
596
597  // Expand non-constant shifts to loops:
598  if (!isa<ConstantSDNode>(N->getOperand(1)))
599    switch (Opc) {
600    default:
601      assert(0 && "Invalid shift opcode!");
602    case ISD::SHL:
603      return DAG.getNode(MSP430ISD::SHL, dl,
604                         VT, N->getOperand(0), N->getOperand(1));
605    case ISD::SRA:
606      return DAG.getNode(MSP430ISD::SRA, dl,
607                         VT, N->getOperand(0), N->getOperand(1));
608    case ISD::SRL:
609      return DAG.getNode(MSP430ISD::SRL, dl,
610                         VT, N->getOperand(0), N->getOperand(1));
611    }
612
613  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
614
615  // Expand the stuff into sequence of shifts.
616  // FIXME: for some shift amounts this might be done better!
617  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
618  SDValue Victim = N->getOperand(0);
619
620  if (Opc == ISD::SRL && ShiftAmount) {
621    // Emit a special goodness here:
622    // srl A, 1 => clrc; rrc A
623    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
624    ShiftAmount -= 1;
625  }
626
627  while (ShiftAmount--)
628    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
629                         dl, VT, Victim);
630
631  return Victim;
632}
633
634SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
635  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
636  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
637
638  // Create the TargetGlobalAddress node, folding in the constant offset.
639  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
640  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
641                     getPointerTy(), Result);
642}
643
644SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
645                                                  SelectionDAG &DAG) {
646  DebugLoc dl = Op.getDebugLoc();
647  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
648  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
649
650  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
651}
652
653static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
654                       ISD::CondCode CC,
655                       DebugLoc dl, SelectionDAG &DAG) {
656  // FIXME: Handle bittests someday
657  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
658
659  // FIXME: Handle jump negative someday
660  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
661  switch (CC) {
662  default: llvm_unreachable("Invalid integer condition!");
663  case ISD::SETEQ:
664    TCC = MSP430CC::COND_E;     // aka COND_Z
665    // Minor optimization: if LHS is a constant, swap operands, then the
666    // constant can be folded into comparison.
667    if (LHS.getOpcode() == ISD::Constant)
668      std::swap(LHS, RHS);
669    break;
670  case ISD::SETNE:
671    TCC = MSP430CC::COND_NE;    // aka COND_NZ
672    // Minor optimization: if LHS is a constant, swap operands, then the
673    // constant can be folded into comparison.
674    if (LHS.getOpcode() == ISD::Constant)
675      std::swap(LHS, RHS);
676    break;
677  case ISD::SETULE:
678    std::swap(LHS, RHS);        // FALLTHROUGH
679  case ISD::SETUGE:
680    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
681    // fold constant into instruction.
682    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
683      LHS = RHS;
684      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
685      TCC = MSP430CC::COND_LO;
686      break;
687    }
688    TCC = MSP430CC::COND_HS;    // aka COND_C
689    break;
690  case ISD::SETUGT:
691    std::swap(LHS, RHS);        // FALLTHROUGH
692  case ISD::SETULT:
693    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
694    // fold constant into instruction.
695    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
696      LHS = RHS;
697      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
698      TCC = MSP430CC::COND_HS;
699      break;
700    }
701    TCC = MSP430CC::COND_LO;    // aka COND_NC
702    break;
703  case ISD::SETLE:
704    std::swap(LHS, RHS);        // FALLTHROUGH
705  case ISD::SETGE:
706    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
707    // fold constant into instruction.
708    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
709      LHS = RHS;
710      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
711      TCC = MSP430CC::COND_L;
712      break;
713    }
714    TCC = MSP430CC::COND_GE;
715    break;
716  case ISD::SETGT:
717    std::swap(LHS, RHS);        // FALLTHROUGH
718  case ISD::SETLT:
719    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
720    // fold constant into instruction.
721    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
722      LHS = RHS;
723      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
724      TCC = MSP430CC::COND_GE;
725      break;
726    }
727    TCC = MSP430CC::COND_L;
728    break;
729  }
730
731  TargetCC = DAG.getConstant(TCC, MVT::i8);
732  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
733}
734
735
736SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
737  SDValue Chain = Op.getOperand(0);
738  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
739  SDValue LHS   = Op.getOperand(2);
740  SDValue RHS   = Op.getOperand(3);
741  SDValue Dest  = Op.getOperand(4);
742  DebugLoc dl   = Op.getDebugLoc();
743
744  SDValue TargetCC;
745  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
746
747  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
748                     Chain, Dest, TargetCC, Flag);
749}
750
751
752SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
753  SDValue LHS   = Op.getOperand(0);
754  SDValue RHS   = Op.getOperand(1);
755  DebugLoc dl   = Op.getDebugLoc();
756
757  // If we are doing an AND and testing against zero, then the CMP
758  // will not be generated.  The AND (or BIT) will generate the condition codes,
759  // but they are different from CMP.
760  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
761  // lowering & isel wouldn't diverge.
762  bool andCC = false;
763  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
764    if (RHSC->isNullValue() && LHS.hasOneUse() &&
765        (LHS.getOpcode() == ISD::AND ||
766         (LHS.getOpcode() == ISD::TRUNCATE &&
767          LHS.getOperand(0).getOpcode() == ISD::AND))) {
768      andCC = true;
769    }
770  }
771  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
772  SDValue TargetCC;
773  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
774
775  // Get the condition codes directly from the status register, if its easy.
776  // Otherwise a branch will be generated.  Note that the AND and BIT
777  // instructions generate different flags than CMP, the carry bit can be used
778  // for NE/EQ.
779  bool Invert = false;
780  bool Shift = false;
781  bool Convert = true;
782  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
783   default:
784    Convert = false;
785    break;
786   case MSP430CC::COND_HS:
787     // Res = SRW & 1, no processing is required
788     break;
789   case MSP430CC::COND_LO:
790     // Res = ~(SRW & 1)
791     Invert = true;
792     break;
793   case MSP430CC::COND_NE:
794     if (andCC) {
795       // C = ~Z, thus Res = SRW & 1, no processing is required
796     } else {
797       // Res = (SRW >> 1) & 1
798       Shift = true;
799     }
800     break;
801   case MSP430CC::COND_E:
802     if (andCC) {
803       // C = ~Z, thus Res = ~(SRW & 1)
804     } else {
805       // Res = ~((SRW >> 1) & 1)
806       Shift = true;
807     }
808     Invert = true;
809     break;
810  }
811  EVT VT = Op.getValueType();
812  SDValue One  = DAG.getConstant(1, VT);
813  if (Convert) {
814    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
815                                    MVT::i16, Flag);
816    if (Shift)
817      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
818      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
819    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
820    if (Invert)
821      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
822    return SR;
823  } else {
824    SDValue Zero = DAG.getConstant(0, VT);
825    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
826    SmallVector<SDValue, 4> Ops;
827    Ops.push_back(One);
828    Ops.push_back(Zero);
829    Ops.push_back(TargetCC);
830    Ops.push_back(Flag);
831    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
832  }
833}
834
835SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
836  SDValue LHS    = Op.getOperand(0);
837  SDValue RHS    = Op.getOperand(1);
838  SDValue TrueV  = Op.getOperand(2);
839  SDValue FalseV = Op.getOperand(3);
840  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
841  DebugLoc dl    = Op.getDebugLoc();
842
843  SDValue TargetCC;
844  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
845
846  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
847  SmallVector<SDValue, 4> Ops;
848  Ops.push_back(TrueV);
849  Ops.push_back(FalseV);
850  Ops.push_back(TargetCC);
851  Ops.push_back(Flag);
852
853  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
854}
855
856SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
857                                               SelectionDAG &DAG) {
858  SDValue Val = Op.getOperand(0);
859  EVT VT      = Op.getValueType();
860  DebugLoc dl = Op.getDebugLoc();
861
862  assert(VT == MVT::i16 && "Only support i16 for now!");
863
864  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
865                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
866                     DAG.getValueType(Val.getValueType()));
867}
868
869SDValue MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
870  MachineFunction &MF = DAG.getMachineFunction();
871  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
872  int ReturnAddrIndex = FuncInfo->getRAIndex();
873
874  if (ReturnAddrIndex == 0) {
875    // Set up a frame object for the return address.
876    uint64_t SlotSize = TD->getPointerSize();
877    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
878                                                           true, false);
879    FuncInfo->setRAIndex(ReturnAddrIndex);
880  }
881
882  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
883}
884
885SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
886  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
887  DebugLoc dl = Op.getDebugLoc();
888
889  if (Depth > 0) {
890    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
891    SDValue Offset =
892      DAG.getConstant(TD->getPointerSize(), MVT::i16);
893    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
894                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
895                                   FrameAddr, Offset),
896                       NULL, 0);
897  }
898
899  // Just load the return address.
900  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
901  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
902                     RetAddrFI, NULL, 0);
903}
904
905SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
906  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
907  MFI->setFrameAddressIsTaken(true);
908  EVT VT = Op.getValueType();
909  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
910  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
911  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
912                                         MSP430::FPW, VT);
913  while (Depth--)
914    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
915  return FrameAddr;
916}
917
918/// getPostIndexedAddressParts - returns true by value, base pointer and
919/// offset pointer and addressing mode by reference if this node can be
920/// combined with a load / store to form a post-indexed load / store.
921bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
922                                                      SDValue &Base,
923                                                      SDValue &Offset,
924                                                      ISD::MemIndexedMode &AM,
925                                                      SelectionDAG &DAG) const {
926
927  LoadSDNode *LD = cast<LoadSDNode>(N);
928  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
929    return false;
930
931  EVT VT = LD->getMemoryVT();
932  if (VT != MVT::i8 && VT != MVT::i16)
933    return false;
934
935  if (Op->getOpcode() != ISD::ADD)
936    return false;
937
938  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
939    uint64_t RHSC = RHS->getZExtValue();
940    if ((VT == MVT::i16 && RHSC != 2) ||
941        (VT == MVT::i8 && RHSC != 1))
942      return false;
943
944    Base = Op->getOperand(0);
945    Offset = DAG.getConstant(RHSC, VT);
946    AM = ISD::POST_INC;
947    return true;
948  }
949
950  return false;
951}
952
953
954const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
955  switch (Opcode) {
956  default: return NULL;
957  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
958  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
959  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
960  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
961  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
962  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
963  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
964  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
965  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
966  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
967  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
968  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
969  }
970}
971
972bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
973                                          const Type *Ty2) const {
974  if (!Ty1->isInteger() || !Ty2->isInteger())
975    return false;
976
977  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
978}
979
980bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
981  if (!VT1.isInteger() || !VT2.isInteger())
982    return false;
983
984  return (VT1.getSizeInBits() > VT2.getSizeInBits());
985}
986
987bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
988  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
989  return 0 && Ty1->isInteger(8) && Ty2->isInteger(16);
990}
991
992bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
993  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
994  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
995}
996
997//===----------------------------------------------------------------------===//
998//  Other Lowering Code
999//===----------------------------------------------------------------------===//
1000
1001MachineBasicBlock*
1002MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1003                                     MachineBasicBlock *BB,
1004                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1005  MachineFunction *F = BB->getParent();
1006  MachineRegisterInfo &RI = F->getRegInfo();
1007  DebugLoc dl = MI->getDebugLoc();
1008  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1009
1010  unsigned Opc;
1011  const TargetRegisterClass * RC;
1012  switch (MI->getOpcode()) {
1013  default:
1014    assert(0 && "Invalid shift opcode!");
1015  case MSP430::Shl8:
1016   Opc = MSP430::SHL8r1;
1017   RC = MSP430::GR8RegisterClass;
1018   break;
1019  case MSP430::Shl16:
1020   Opc = MSP430::SHL16r1;
1021   RC = MSP430::GR16RegisterClass;
1022   break;
1023  case MSP430::Sra8:
1024   Opc = MSP430::SAR8r1;
1025   RC = MSP430::GR8RegisterClass;
1026   break;
1027  case MSP430::Sra16:
1028   Opc = MSP430::SAR16r1;
1029   RC = MSP430::GR16RegisterClass;
1030   break;
1031  case MSP430::Srl8:
1032   Opc = MSP430::SAR8r1c;
1033   RC = MSP430::GR8RegisterClass;
1034   break;
1035  case MSP430::Srl16:
1036   Opc = MSP430::SAR16r1c;
1037   RC = MSP430::GR16RegisterClass;
1038   break;
1039  }
1040
1041  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1042  MachineFunction::iterator I = BB;
1043  ++I;
1044
1045  // Create loop block
1046  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1047  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1048
1049  F->insert(I, LoopBB);
1050  F->insert(I, RemBB);
1051
1052  // Update machine-CFG edges by transferring all successors of the current
1053  // block to the block containing instructions after shift.
1054  RemBB->transferSuccessors(BB);
1055
1056  // Inform sdisel of the edge changes.
1057  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1058         SE = BB->succ_end(); SI != SE; ++SI)
1059    EM->insert(std::make_pair(*SI, RemBB));
1060
1061  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1062  BB->addSuccessor(LoopBB);
1063  BB->addSuccessor(RemBB);
1064  LoopBB->addSuccessor(RemBB);
1065  LoopBB->addSuccessor(LoopBB);
1066
1067  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1068  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1069  unsigned ShiftReg = RI.createVirtualRegister(RC);
1070  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1071  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1072  unsigned SrcReg = MI->getOperand(1).getReg();
1073  unsigned DstReg = MI->getOperand(0).getReg();
1074
1075  // BB:
1076  // cmp 0, N
1077  // je RemBB
1078  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1079    .addReg(ShiftAmtSrcReg).addImm(0);
1080  BuildMI(BB, dl, TII.get(MSP430::JCC))
1081    .addMBB(RemBB)
1082    .addImm(MSP430CC::COND_E);
1083
1084  // LoopBB:
1085  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1086  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1087  // ShiftReg2 = shift ShiftReg
1088  // ShiftAmt2 = ShiftAmt - 1;
1089  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1090    .addReg(SrcReg).addMBB(BB)
1091    .addReg(ShiftReg2).addMBB(LoopBB);
1092  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1093    .addReg(ShiftAmtSrcReg).addMBB(BB)
1094    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1095  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1096    .addReg(ShiftReg);
1097  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1098    .addReg(ShiftAmtReg).addImm(1);
1099  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1100    .addMBB(LoopBB)
1101    .addImm(MSP430CC::COND_NE);
1102
1103  // RemBB:
1104  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1105  BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
1106    .addReg(SrcReg).addMBB(BB)
1107    .addReg(ShiftReg2).addMBB(LoopBB);
1108
1109  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1110  return RemBB;
1111}
1112
1113MachineBasicBlock*
1114MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1115                                                  MachineBasicBlock *BB,
1116                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1117  unsigned Opc = MI->getOpcode();
1118
1119  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1120      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1121      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1122    return EmitShiftInstr(MI, BB, EM);
1123
1124  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1125  DebugLoc dl = MI->getDebugLoc();
1126
1127  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1128         "Unexpected instr type to insert");
1129
1130  // To "insert" a SELECT instruction, we actually have to insert the diamond
1131  // control-flow pattern.  The incoming instruction knows the destination vreg
1132  // to set, the condition code register to branch on, the true/false values to
1133  // select between, and a branch opcode to use.
1134  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1135  MachineFunction::iterator I = BB;
1136  ++I;
1137
1138  //  thisMBB:
1139  //  ...
1140  //   TrueVal = ...
1141  //   cmpTY ccX, r1, r2
1142  //   jCC copy1MBB
1143  //   fallthrough --> copy0MBB
1144  MachineBasicBlock *thisMBB = BB;
1145  MachineFunction *F = BB->getParent();
1146  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1147  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1148  BuildMI(BB, dl, TII.get(MSP430::JCC))
1149    .addMBB(copy1MBB)
1150    .addImm(MI->getOperand(3).getImm());
1151  F->insert(I, copy0MBB);
1152  F->insert(I, copy1MBB);
1153  // Inform sdisel of the edge changes.
1154  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1155         SE = BB->succ_end(); SI != SE; ++SI)
1156    EM->insert(std::make_pair(*SI, copy1MBB));
1157  // Update machine-CFG edges by transferring all successors of the current
1158  // block to the new block which will contain the Phi node for the select.
1159  copy1MBB->transferSuccessors(BB);
1160  // Next, add the true and fallthrough blocks as its successors.
1161  BB->addSuccessor(copy0MBB);
1162  BB->addSuccessor(copy1MBB);
1163
1164  //  copy0MBB:
1165  //   %FalseValue = ...
1166  //   # fallthrough to copy1MBB
1167  BB = copy0MBB;
1168
1169  // Update machine-CFG edges
1170  BB->addSuccessor(copy1MBB);
1171
1172  //  copy1MBB:
1173  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1174  //  ...
1175  BB = copy1MBB;
1176  BuildMI(BB, dl, TII.get(MSP430::PHI),
1177          MI->getOperand(0).getReg())
1178    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1179    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1180
1181  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1182  return BB;
1183}
1184