MSP430ISelLowering.cpp revision 27253f5edd04791bfbd0b5dd6e228be1d8071fce 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430Subtarget.h"
20#include "MSP430TargetMachine.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/SelectionDAGISel.h"
27#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28#include "llvm/CodeGen/ValueTypes.h"
29#include "llvm/IR/CallingConv.h"
30#include "llvm/IR/DerivedTypes.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/GlobalAlias.h"
33#include "llvm/IR/GlobalVariable.h"
34#include "llvm/IR/Intrinsics.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41typedef enum {
42  NoHWMult,
43  HWMultIntr,
44  HWMultNoIntr
45} HWMultUseMode;
46
47static cl::opt<HWMultUseMode>
48HWMultMode("msp430-hwmult-mode",
49           cl::desc("Hardware multiplier use mode"),
50           cl::init(HWMultNoIntr),
51           cl::values(
52             clEnumValN(NoHWMult, "no",
53                "Do not use hardware multiplier"),
54             clEnumValN(HWMultIntr, "interrupts",
55                "Assume hardware multiplier can be used inside interrupts"),
56             clEnumValN(HWMultNoIntr, "use",
57                "Assume hardware multiplier cannot be used inside interrupts"),
58             clEnumValEnd));
59
60MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
61  TargetLowering(tm, new TargetLoweringObjectFileELF()),
62  Subtarget(*tm.getSubtargetImpl()) {
63
64  TD = getDataLayout();
65
66  // Set up the register classes.
67  addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
68  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
69
70  // Compute derived properties from the register classes
71  computeRegisterProperties();
72
73  // Provide all sorts of operation actions
74
75  // Division is expensive
76  setIntDivIsCheap(false);
77
78  setStackPointerRegisterToSaveRestore(MSP430::SPW);
79  setBooleanContents(ZeroOrOneBooleanContent);
80  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
81
82  // We have post-incremented loads / stores.
83  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
85
86  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
88  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
89  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
90  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
91
92  // We don't have any truncstores
93  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
96  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
97  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
98  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
99  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
100  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
101  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
102  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
103  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
104  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
105  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
106  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
107  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
108  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
110  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
111  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
112  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
113  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
114  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
115  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
116  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
117  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
118  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
119  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
123  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
124  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i8,    Expand);
125  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i16,   Expand);
126  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
128  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i8,    Expand);
129  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i16,   Expand);
130  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
131  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
132
133  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
134  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
135  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
139
140  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
141
142  // FIXME: Implement efficiently multiplication by a constant
143  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
144  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
145  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
146  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
147  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
148  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
149  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
150  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
151  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
152  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
153
154  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
155  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
156  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
157  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
158  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
159  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
160  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
161  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
162  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
163  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
164  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
165  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
166
167  // varargs support
168  setOperationAction(ISD::VASTART,          MVT::Other, Custom);
169  setOperationAction(ISD::VAARG,            MVT::Other, Expand);
170  setOperationAction(ISD::VAEND,            MVT::Other, Expand);
171  setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
172  setOperationAction(ISD::JumpTable,        MVT::i16,   Custom);
173
174  // Libcalls names.
175  if (HWMultMode == HWMultIntr) {
176    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
177    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
178  } else if (HWMultMode == HWMultNoIntr) {
179    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
180    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
181  }
182
183  setMinFunctionAlignment(1);
184  setPrefFunctionAlignment(2);
185}
186
187SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
188                                             SelectionDAG &DAG) const {
189  switch (Op.getOpcode()) {
190  case ISD::SHL: // FALLTHROUGH
191  case ISD::SRL:
192  case ISD::SRA:              return LowerShifts(Op, DAG);
193  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
194  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
195  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
196  case ISD::SETCC:            return LowerSETCC(Op, DAG);
197  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
198  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
199  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
200  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
201  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
202  case ISD::VASTART:          return LowerVASTART(Op, DAG);
203  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
204  default:
205    llvm_unreachable("unimplemented operand");
206  }
207}
208
209//===----------------------------------------------------------------------===//
210//                       MSP430 Inline Assembly Support
211//===----------------------------------------------------------------------===//
212
213/// getConstraintType - Given a constraint letter, return the type of
214/// constraint it is for this target.
215TargetLowering::ConstraintType
216MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
217  if (Constraint.size() == 1) {
218    switch (Constraint[0]) {
219    case 'r':
220      return C_RegisterClass;
221    default:
222      break;
223    }
224  }
225  return TargetLowering::getConstraintType(Constraint);
226}
227
228std::pair<unsigned, const TargetRegisterClass*>
229MSP430TargetLowering::
230getRegForInlineAsmConstraint(const std::string &Constraint,
231                             MVT VT) const {
232  if (Constraint.size() == 1) {
233    // GCC Constraint Letters
234    switch (Constraint[0]) {
235    default: break;
236    case 'r':   // GENERAL_REGS
237      if (VT == MVT::i8)
238        return std::make_pair(0U, &MSP430::GR8RegClass);
239
240      return std::make_pair(0U, &MSP430::GR16RegClass);
241    }
242  }
243
244  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
245}
246
247//===----------------------------------------------------------------------===//
248//                      Calling Convention Implementation
249//===----------------------------------------------------------------------===//
250
251#include "MSP430GenCallingConv.inc"
252
253SDValue
254MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
255                                           CallingConv::ID CallConv,
256                                           bool isVarArg,
257                                           const SmallVectorImpl<ISD::InputArg>
258                                             &Ins,
259                                           SDLoc dl,
260                                           SelectionDAG &DAG,
261                                           SmallVectorImpl<SDValue> &InVals)
262                                             const {
263
264  switch (CallConv) {
265  default:
266    llvm_unreachable("Unsupported calling convention");
267  case CallingConv::C:
268  case CallingConv::Fast:
269    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
270  case CallingConv::MSP430_INTR:
271    if (Ins.empty())
272      return Chain;
273    report_fatal_error("ISRs cannot have arguments");
274  }
275}
276
277SDValue
278MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
279                                SmallVectorImpl<SDValue> &InVals) const {
280  SelectionDAG &DAG                     = CLI.DAG;
281  SDLoc &dl                             = CLI.DL;
282  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
283  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
284  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
285  SDValue Chain                         = CLI.Chain;
286  SDValue Callee                        = CLI.Callee;
287  bool &isTailCall                      = CLI.IsTailCall;
288  CallingConv::ID CallConv              = CLI.CallConv;
289  bool isVarArg                         = CLI.IsVarArg;
290
291  // MSP430 target does not yet support tail call optimization.
292  isTailCall = false;
293
294  switch (CallConv) {
295  default:
296    llvm_unreachable("Unsupported calling convention");
297  case CallingConv::Fast:
298  case CallingConv::C:
299    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
300                          Outs, OutVals, Ins, dl, DAG, InVals);
301  case CallingConv::MSP430_INTR:
302    report_fatal_error("ISRs cannot be called directly");
303  }
304}
305
306/// LowerCCCArguments - transform physical registers into virtual registers and
307/// generate load operations for arguments places on the stack.
308// FIXME: struct return stuff
309SDValue
310MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
311                                        CallingConv::ID CallConv,
312                                        bool isVarArg,
313                                        const SmallVectorImpl<ISD::InputArg>
314                                          &Ins,
315                                        SDLoc dl,
316                                        SelectionDAG &DAG,
317                                        SmallVectorImpl<SDValue> &InVals)
318                                          const {
319  MachineFunction &MF = DAG.getMachineFunction();
320  MachineFrameInfo *MFI = MF.getFrameInfo();
321  MachineRegisterInfo &RegInfo = MF.getRegInfo();
322  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
323
324  // Assign locations to all of the incoming arguments.
325  SmallVector<CCValAssign, 16> ArgLocs;
326  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
327                 getTargetMachine(), ArgLocs, *DAG.getContext());
328  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
329
330  // Create frame index for the start of the first vararg value
331  if (isVarArg) {
332    unsigned Offset = CCInfo.getNextStackOffset();
333    FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
334  }
335
336  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
337    CCValAssign &VA = ArgLocs[i];
338    if (VA.isRegLoc()) {
339      // Arguments passed in registers
340      EVT RegVT = VA.getLocVT();
341      switch (RegVT.getSimpleVT().SimpleTy) {
342      default:
343        {
344#ifndef NDEBUG
345          errs() << "LowerFormalArguments Unhandled argument type: "
346               << RegVT.getSimpleVT().SimpleTy << "\n";
347#endif
348          llvm_unreachable(0);
349        }
350      case MVT::i16:
351        unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
352        RegInfo.addLiveIn(VA.getLocReg(), VReg);
353        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
354
355        // If this is an 8-bit value, it is really passed promoted to 16
356        // bits. Insert an assert[sz]ext to capture this, then truncate to the
357        // right size.
358        if (VA.getLocInfo() == CCValAssign::SExt)
359          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
360                                 DAG.getValueType(VA.getValVT()));
361        else if (VA.getLocInfo() == CCValAssign::ZExt)
362          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
363                                 DAG.getValueType(VA.getValVT()));
364
365        if (VA.getLocInfo() != CCValAssign::Full)
366          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
367
368        InVals.push_back(ArgValue);
369      }
370    } else {
371      // Sanity check
372      assert(VA.isMemLoc());
373
374      SDValue InVal;
375      ISD::ArgFlagsTy Flags = Ins[i].Flags;
376
377      if (Flags.isByVal()) {
378        int FI = MFI->CreateFixedObject(Flags.getByValSize(),
379                                        VA.getLocMemOffset(), true);
380        InVal = DAG.getFrameIndex(FI, getPointerTy());
381      } else {
382        // Load the argument to a virtual register
383        unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
384        if (ObjSize > 2) {
385            errs() << "LowerFormalArguments Unhandled argument type: "
386                << EVT(VA.getLocVT()).getEVTString()
387                << "\n";
388        }
389        // Create the frame index object for this incoming parameter...
390        int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
391
392        // Create the SelectionDAG nodes corresponding to a load
393        //from this parameter
394        SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
395        InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
396                            MachinePointerInfo::getFixedStack(FI),
397                            false, false, false, 0);
398      }
399
400      InVals.push_back(InVal);
401    }
402  }
403
404  return Chain;
405}
406
407SDValue
408MSP430TargetLowering::LowerReturn(SDValue Chain,
409                                  CallingConv::ID CallConv, bool isVarArg,
410                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
411                                  const SmallVectorImpl<SDValue> &OutVals,
412                                  SDLoc dl, SelectionDAG &DAG) const {
413
414  // CCValAssign - represent the assignment of the return value to a location
415  SmallVector<CCValAssign, 16> RVLocs;
416
417  // ISRs cannot return any value.
418  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
419    report_fatal_error("ISRs cannot return any value");
420
421  // CCState - Info about the registers and stack slot.
422  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
423                 getTargetMachine(), RVLocs, *DAG.getContext());
424
425  // Analize return values.
426  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
427
428  SDValue Flag;
429  SmallVector<SDValue, 4> RetOps(1, Chain);
430
431  // Copy the result values into the output registers.
432  for (unsigned i = 0; i != RVLocs.size(); ++i) {
433    CCValAssign &VA = RVLocs[i];
434    assert(VA.isRegLoc() && "Can only return in registers!");
435
436    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
437                             OutVals[i], Flag);
438
439    // Guarantee that all emitted copies are stuck together,
440    // avoiding something bad.
441    Flag = Chain.getValue(1);
442    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
443  }
444
445  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
446                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
447
448  RetOps[0] = Chain;  // Update chain.
449
450  // Add the flag if we have it.
451  if (Flag.getNode())
452    RetOps.push_back(Flag);
453
454  return DAG.getNode(Opc, dl, MVT::Other, &RetOps[0], RetOps.size());
455}
456
457/// LowerCCCCallTo - functions arguments are copied from virtual regs to
458/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
459/// TODO: sret.
460SDValue
461MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
462                                     CallingConv::ID CallConv, bool isVarArg,
463                                     bool isTailCall,
464                                     const SmallVectorImpl<ISD::OutputArg>
465                                       &Outs,
466                                     const SmallVectorImpl<SDValue> &OutVals,
467                                     const SmallVectorImpl<ISD::InputArg> &Ins,
468                                     SDLoc dl, SelectionDAG &DAG,
469                                     SmallVectorImpl<SDValue> &InVals) const {
470  // Analyze operands of the call, assigning locations to each operand.
471  SmallVector<CCValAssign, 16> ArgLocs;
472  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
473                 getTargetMachine(), ArgLocs, *DAG.getContext());
474
475  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
476
477  // Get a count of how many bytes are to be pushed on the stack.
478  unsigned NumBytes = CCInfo.getNextStackOffset();
479
480  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
481                                                      getPointerTy(), true),
482                               dl);
483
484  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
485  SmallVector<SDValue, 12> MemOpChains;
486  SDValue StackPtr;
487
488  // Walk the register/memloc assignments, inserting copies/loads.
489  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
490    CCValAssign &VA = ArgLocs[i];
491
492    SDValue Arg = OutVals[i];
493
494    // Promote the value if needed.
495    switch (VA.getLocInfo()) {
496      default: llvm_unreachable("Unknown loc info!");
497      case CCValAssign::Full: break;
498      case CCValAssign::SExt:
499        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
500        break;
501      case CCValAssign::ZExt:
502        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
503        break;
504      case CCValAssign::AExt:
505        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
506        break;
507    }
508
509    // Arguments that can be passed on register must be kept at RegsToPass
510    // vector
511    if (VA.isRegLoc()) {
512      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
513    } else {
514      assert(VA.isMemLoc());
515
516      if (StackPtr.getNode() == 0)
517        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
518
519      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
520                                   StackPtr,
521                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
522
523      SDValue MemOp;
524      ISD::ArgFlagsTy Flags = Outs[i].Flags;
525
526      if (Flags.isByVal()) {
527        SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
528        MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
529                              Flags.getByValAlign(),
530                              /*isVolatile*/false,
531                              /*AlwaysInline=*/true,
532                              MachinePointerInfo(),
533                              MachinePointerInfo());
534      } else {
535        MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
536                             false, false, 0);
537      }
538
539      MemOpChains.push_back(MemOp);
540    }
541  }
542
543  // Transform all store nodes into one single node because all store nodes are
544  // independent of each other.
545  if (!MemOpChains.empty())
546    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
547                        &MemOpChains[0], MemOpChains.size());
548
549  // Build a sequence of copy-to-reg nodes chained together with token chain and
550  // flag operands which copy the outgoing args into registers.  The InFlag in
551  // necessary since all emitted instructions must be stuck together.
552  SDValue InFlag;
553  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
554    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
555                             RegsToPass[i].second, InFlag);
556    InFlag = Chain.getValue(1);
557  }
558
559  // If the callee is a GlobalAddress node (quite common, every direct call is)
560  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
561  // Likewise ExternalSymbol -> TargetExternalSymbol.
562  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
563    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
564  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
565    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
566
567  // Returns a chain & a flag for retval copy to use.
568  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
569  SmallVector<SDValue, 8> Ops;
570  Ops.push_back(Chain);
571  Ops.push_back(Callee);
572
573  // Add argument registers to the end of the list so that they are
574  // known live into the call.
575  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
576    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
577                                  RegsToPass[i].second.getValueType()));
578
579  if (InFlag.getNode())
580    Ops.push_back(InFlag);
581
582  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
583  InFlag = Chain.getValue(1);
584
585  // Create the CALLSEQ_END node.
586  Chain = DAG.getCALLSEQ_END(Chain,
587                             DAG.getConstant(NumBytes, getPointerTy(), true),
588                             DAG.getConstant(0, getPointerTy(), true),
589                             InFlag, dl);
590  InFlag = Chain.getValue(1);
591
592  // Handle result values, copying them out of physregs into vregs that we
593  // return.
594  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
595                         DAG, InVals);
596}
597
598/// LowerCallResult - Lower the result values of a call into the
599/// appropriate copies out of appropriate physical registers.
600///
601SDValue
602MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
603                                      CallingConv::ID CallConv, bool isVarArg,
604                                      const SmallVectorImpl<ISD::InputArg> &Ins,
605                                      SDLoc dl, SelectionDAG &DAG,
606                                      SmallVectorImpl<SDValue> &InVals) const {
607
608  // Assign locations to each value returned by this call.
609  SmallVector<CCValAssign, 16> RVLocs;
610  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
611                 getTargetMachine(), RVLocs, *DAG.getContext());
612
613  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
614
615  // Copy all of the result registers out of their specified physreg.
616  for (unsigned i = 0; i != RVLocs.size(); ++i) {
617    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
618                               RVLocs[i].getValVT(), InFlag).getValue(1);
619    InFlag = Chain.getValue(2);
620    InVals.push_back(Chain.getValue(0));
621  }
622
623  return Chain;
624}
625
626SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
627                                          SelectionDAG &DAG) const {
628  unsigned Opc = Op.getOpcode();
629  SDNode* N = Op.getNode();
630  EVT VT = Op.getValueType();
631  SDLoc dl(N);
632
633  // Expand non-constant shifts to loops:
634  if (!isa<ConstantSDNode>(N->getOperand(1)))
635    switch (Opc) {
636    default: llvm_unreachable("Invalid shift opcode!");
637    case ISD::SHL:
638      return DAG.getNode(MSP430ISD::SHL, dl,
639                         VT, N->getOperand(0), N->getOperand(1));
640    case ISD::SRA:
641      return DAG.getNode(MSP430ISD::SRA, dl,
642                         VT, N->getOperand(0), N->getOperand(1));
643    case ISD::SRL:
644      return DAG.getNode(MSP430ISD::SRL, dl,
645                         VT, N->getOperand(0), N->getOperand(1));
646    }
647
648  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
649
650  // Expand the stuff into sequence of shifts.
651  // FIXME: for some shift amounts this might be done better!
652  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
653  SDValue Victim = N->getOperand(0);
654
655  if (Opc == ISD::SRL && ShiftAmount) {
656    // Emit a special goodness here:
657    // srl A, 1 => clrc; rrc A
658    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
659    ShiftAmount -= 1;
660  }
661
662  while (ShiftAmount--)
663    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
664                         dl, VT, Victim);
665
666  return Victim;
667}
668
669SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
670                                                 SelectionDAG &DAG) const {
671  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
672  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
673
674  // Create the TargetGlobalAddress node, folding in the constant offset.
675  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
676                                              getPointerTy(), Offset);
677  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op),
678                     getPointerTy(), Result);
679}
680
681SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
682                                                  SelectionDAG &DAG) const {
683  SDLoc dl(Op);
684  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
685  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
686
687  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
688}
689
690SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
691                                                SelectionDAG &DAG) const {
692  SDLoc dl(Op);
693  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
694  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
695
696  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
697}
698
699static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
700                       ISD::CondCode CC,
701                       SDLoc dl, SelectionDAG &DAG) {
702  // FIXME: Handle bittests someday
703  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
704
705  // FIXME: Handle jump negative someday
706  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
707  switch (CC) {
708  default: llvm_unreachable("Invalid integer condition!");
709  case ISD::SETEQ:
710    TCC = MSP430CC::COND_E;     // aka COND_Z
711    // Minor optimization: if LHS is a constant, swap operands, then the
712    // constant can be folded into comparison.
713    if (LHS.getOpcode() == ISD::Constant)
714      std::swap(LHS, RHS);
715    break;
716  case ISD::SETNE:
717    TCC = MSP430CC::COND_NE;    // aka COND_NZ
718    // Minor optimization: if LHS is a constant, swap operands, then the
719    // constant can be folded into comparison.
720    if (LHS.getOpcode() == ISD::Constant)
721      std::swap(LHS, RHS);
722    break;
723  case ISD::SETULE:
724    std::swap(LHS, RHS);        // FALLTHROUGH
725  case ISD::SETUGE:
726    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
727    // fold constant into instruction.
728    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
729      LHS = RHS;
730      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
731      TCC = MSP430CC::COND_LO;
732      break;
733    }
734    TCC = MSP430CC::COND_HS;    // aka COND_C
735    break;
736  case ISD::SETUGT:
737    std::swap(LHS, RHS);        // FALLTHROUGH
738  case ISD::SETULT:
739    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
740    // fold constant into instruction.
741    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
742      LHS = RHS;
743      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
744      TCC = MSP430CC::COND_HS;
745      break;
746    }
747    TCC = MSP430CC::COND_LO;    // aka COND_NC
748    break;
749  case ISD::SETLE:
750    std::swap(LHS, RHS);        // FALLTHROUGH
751  case ISD::SETGE:
752    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
753    // fold constant into instruction.
754    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
755      LHS = RHS;
756      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
757      TCC = MSP430CC::COND_L;
758      break;
759    }
760    TCC = MSP430CC::COND_GE;
761    break;
762  case ISD::SETGT:
763    std::swap(LHS, RHS);        // FALLTHROUGH
764  case ISD::SETLT:
765    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
766    // fold constant into instruction.
767    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
768      LHS = RHS;
769      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
770      TCC = MSP430CC::COND_GE;
771      break;
772    }
773    TCC = MSP430CC::COND_L;
774    break;
775  }
776
777  TargetCC = DAG.getConstant(TCC, MVT::i8);
778  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
779}
780
781
782SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
783  SDValue Chain = Op.getOperand(0);
784  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
785  SDValue LHS   = Op.getOperand(2);
786  SDValue RHS   = Op.getOperand(3);
787  SDValue Dest  = Op.getOperand(4);
788  SDLoc dl  (Op);
789
790  SDValue TargetCC;
791  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
792
793  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
794                     Chain, Dest, TargetCC, Flag);
795}
796
797SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
798  SDValue LHS   = Op.getOperand(0);
799  SDValue RHS   = Op.getOperand(1);
800  SDLoc dl  (Op);
801
802  // If we are doing an AND and testing against zero, then the CMP
803  // will not be generated.  The AND (or BIT) will generate the condition codes,
804  // but they are different from CMP.
805  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
806  // lowering & isel wouldn't diverge.
807  bool andCC = false;
808  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
809    if (RHSC->isNullValue() && LHS.hasOneUse() &&
810        (LHS.getOpcode() == ISD::AND ||
811         (LHS.getOpcode() == ISD::TRUNCATE &&
812          LHS.getOperand(0).getOpcode() == ISD::AND))) {
813      andCC = true;
814    }
815  }
816  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
817  SDValue TargetCC;
818  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
819
820  // Get the condition codes directly from the status register, if its easy.
821  // Otherwise a branch will be generated.  Note that the AND and BIT
822  // instructions generate different flags than CMP, the carry bit can be used
823  // for NE/EQ.
824  bool Invert = false;
825  bool Shift = false;
826  bool Convert = true;
827  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
828   default:
829    Convert = false;
830    break;
831   case MSP430CC::COND_HS:
832     // Res = SRW & 1, no processing is required
833     break;
834   case MSP430CC::COND_LO:
835     // Res = ~(SRW & 1)
836     Invert = true;
837     break;
838   case MSP430CC::COND_NE:
839     if (andCC) {
840       // C = ~Z, thus Res = SRW & 1, no processing is required
841     } else {
842       // Res = ~((SRW >> 1) & 1)
843       Shift = true;
844       Invert = true;
845     }
846     break;
847   case MSP430CC::COND_E:
848     Shift = true;
849     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
850     // Res = (SRW >> 1) & 1 is 1 word shorter.
851     break;
852  }
853  EVT VT = Op.getValueType();
854  SDValue One  = DAG.getConstant(1, VT);
855  if (Convert) {
856    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
857                                    MVT::i16, Flag);
858    if (Shift)
859      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
860      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
861    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
862    if (Invert)
863      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
864    return SR;
865  } else {
866    SDValue Zero = DAG.getConstant(0, VT);
867    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
868    SmallVector<SDValue, 4> Ops;
869    Ops.push_back(One);
870    Ops.push_back(Zero);
871    Ops.push_back(TargetCC);
872    Ops.push_back(Flag);
873    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
874  }
875}
876
877SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
878                                             SelectionDAG &DAG) const {
879  SDValue LHS    = Op.getOperand(0);
880  SDValue RHS    = Op.getOperand(1);
881  SDValue TrueV  = Op.getOperand(2);
882  SDValue FalseV = Op.getOperand(3);
883  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
884  SDLoc dl   (Op);
885
886  SDValue TargetCC;
887  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
888
889  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
890  SmallVector<SDValue, 4> Ops;
891  Ops.push_back(TrueV);
892  Ops.push_back(FalseV);
893  Ops.push_back(TargetCC);
894  Ops.push_back(Flag);
895
896  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
897}
898
899SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
900                                               SelectionDAG &DAG) const {
901  SDValue Val = Op.getOperand(0);
902  EVT VT      = Op.getValueType();
903  SDLoc dl(Op);
904
905  assert(VT == MVT::i16 && "Only support i16 for now!");
906
907  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
908                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
909                     DAG.getValueType(Val.getValueType()));
910}
911
912SDValue
913MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
914  MachineFunction &MF = DAG.getMachineFunction();
915  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
916  int ReturnAddrIndex = FuncInfo->getRAIndex();
917
918  if (ReturnAddrIndex == 0) {
919    // Set up a frame object for the return address.
920    uint64_t SlotSize = TD->getPointerSize();
921    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
922                                                           true);
923    FuncInfo->setRAIndex(ReturnAddrIndex);
924  }
925
926  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
927}
928
929SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
930                                              SelectionDAG &DAG) const {
931  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
932  MFI->setReturnAddressIsTaken(true);
933
934  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
935  SDLoc dl(Op);
936
937  if (Depth > 0) {
938    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
939    SDValue Offset =
940      DAG.getConstant(TD->getPointerSize(), MVT::i16);
941    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
942                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
943                                   FrameAddr, Offset),
944                       MachinePointerInfo(), false, false, false, 0);
945  }
946
947  // Just load the return address.
948  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
949  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
950                     RetAddrFI, MachinePointerInfo(), false, false, false, 0);
951}
952
953SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
954                                             SelectionDAG &DAG) const {
955  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
956  MFI->setFrameAddressIsTaken(true);
957
958  EVT VT = Op.getValueType();
959  SDLoc dl(Op);  // FIXME probably not meaningful
960  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
961  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
962                                         MSP430::FPW, VT);
963  while (Depth--)
964    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
965                            MachinePointerInfo(),
966                            false, false, false, 0);
967  return FrameAddr;
968}
969
970SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
971                                           SelectionDAG &DAG) const {
972  MachineFunction &MF = DAG.getMachineFunction();
973  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
974
975  // Frame index of first vararg argument
976  SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
977                                         getPointerTy());
978  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
979
980  // Create a store of the frame index to the location operand
981  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex,
982                      Op.getOperand(1), MachinePointerInfo(SV),
983                      false, false, 0);
984}
985
986SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
987                                             SelectionDAG &DAG) const {
988    JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
989    SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
990    Result.getNode()->setDebugLoc(JT->getDebugLoc());
991    return Result;
992}
993
994/// getPostIndexedAddressParts - returns true by value, base pointer and
995/// offset pointer and addressing mode by reference if this node can be
996/// combined with a load / store to form a post-indexed load / store.
997bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
998                                                      SDValue &Base,
999                                                      SDValue &Offset,
1000                                                      ISD::MemIndexedMode &AM,
1001                                                      SelectionDAG &DAG) const {
1002
1003  LoadSDNode *LD = cast<LoadSDNode>(N);
1004  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1005    return false;
1006
1007  EVT VT = LD->getMemoryVT();
1008  if (VT != MVT::i8 && VT != MVT::i16)
1009    return false;
1010
1011  if (Op->getOpcode() != ISD::ADD)
1012    return false;
1013
1014  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1015    uint64_t RHSC = RHS->getZExtValue();
1016    if ((VT == MVT::i16 && RHSC != 2) ||
1017        (VT == MVT::i8 && RHSC != 1))
1018      return false;
1019
1020    Base = Op->getOperand(0);
1021    Offset = DAG.getConstant(RHSC, VT);
1022    AM = ISD::POST_INC;
1023    return true;
1024  }
1025
1026  return false;
1027}
1028
1029
1030const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1031  switch (Opcode) {
1032  default: return NULL;
1033  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1034  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1035  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1036  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1037  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1038  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1039  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1040  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1041  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1042  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1043  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
1044  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
1045  }
1046}
1047
1048bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1049                                          Type *Ty2) const {
1050  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1051    return false;
1052
1053  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1054}
1055
1056bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1057  if (!VT1.isInteger() || !VT2.isInteger())
1058    return false;
1059
1060  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1061}
1062
1063bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1064  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1065  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1066}
1067
1068bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1069  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1070  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1071}
1072
1073bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1074  return isZExtFree(Val.getValueType(), VT2);
1075}
1076
1077//===----------------------------------------------------------------------===//
1078//  Other Lowering Code
1079//===----------------------------------------------------------------------===//
1080
1081MachineBasicBlock*
1082MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1083                                     MachineBasicBlock *BB) const {
1084  MachineFunction *F = BB->getParent();
1085  MachineRegisterInfo &RI = F->getRegInfo();
1086  DebugLoc dl = MI->getDebugLoc();
1087  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1088
1089  unsigned Opc;
1090  const TargetRegisterClass * RC;
1091  switch (MI->getOpcode()) {
1092  default: llvm_unreachable("Invalid shift opcode!");
1093  case MSP430::Shl8:
1094   Opc = MSP430::SHL8r1;
1095   RC = &MSP430::GR8RegClass;
1096   break;
1097  case MSP430::Shl16:
1098   Opc = MSP430::SHL16r1;
1099   RC = &MSP430::GR16RegClass;
1100   break;
1101  case MSP430::Sra8:
1102   Opc = MSP430::SAR8r1;
1103   RC = &MSP430::GR8RegClass;
1104   break;
1105  case MSP430::Sra16:
1106   Opc = MSP430::SAR16r1;
1107   RC = &MSP430::GR16RegClass;
1108   break;
1109  case MSP430::Srl8:
1110   Opc = MSP430::SAR8r1c;
1111   RC = &MSP430::GR8RegClass;
1112   break;
1113  case MSP430::Srl16:
1114   Opc = MSP430::SAR16r1c;
1115   RC = &MSP430::GR16RegClass;
1116   break;
1117  }
1118
1119  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1120  MachineFunction::iterator I = BB;
1121  ++I;
1122
1123  // Create loop block
1124  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1125  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1126
1127  F->insert(I, LoopBB);
1128  F->insert(I, RemBB);
1129
1130  // Update machine-CFG edges by transferring all successors of the current
1131  // block to the block containing instructions after shift.
1132  RemBB->splice(RemBB->begin(), BB,
1133                llvm::next(MachineBasicBlock::iterator(MI)),
1134                BB->end());
1135  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1136
1137  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1138  BB->addSuccessor(LoopBB);
1139  BB->addSuccessor(RemBB);
1140  LoopBB->addSuccessor(RemBB);
1141  LoopBB->addSuccessor(LoopBB);
1142
1143  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1144  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1145  unsigned ShiftReg = RI.createVirtualRegister(RC);
1146  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1147  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1148  unsigned SrcReg = MI->getOperand(1).getReg();
1149  unsigned DstReg = MI->getOperand(0).getReg();
1150
1151  // BB:
1152  // cmp 0, N
1153  // je RemBB
1154  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1155    .addReg(ShiftAmtSrcReg).addImm(0);
1156  BuildMI(BB, dl, TII.get(MSP430::JCC))
1157    .addMBB(RemBB)
1158    .addImm(MSP430CC::COND_E);
1159
1160  // LoopBB:
1161  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1162  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1163  // ShiftReg2 = shift ShiftReg
1164  // ShiftAmt2 = ShiftAmt - 1;
1165  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1166    .addReg(SrcReg).addMBB(BB)
1167    .addReg(ShiftReg2).addMBB(LoopBB);
1168  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1169    .addReg(ShiftAmtSrcReg).addMBB(BB)
1170    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1171  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1172    .addReg(ShiftReg);
1173  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1174    .addReg(ShiftAmtReg).addImm(1);
1175  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1176    .addMBB(LoopBB)
1177    .addImm(MSP430CC::COND_NE);
1178
1179  // RemBB:
1180  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1181  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1182    .addReg(SrcReg).addMBB(BB)
1183    .addReg(ShiftReg2).addMBB(LoopBB);
1184
1185  MI->eraseFromParent();   // The pseudo instruction is gone now.
1186  return RemBB;
1187}
1188
1189MachineBasicBlock*
1190MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1191                                                  MachineBasicBlock *BB) const {
1192  unsigned Opc = MI->getOpcode();
1193
1194  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1195      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1196      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1197    return EmitShiftInstr(MI, BB);
1198
1199  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1200  DebugLoc dl = MI->getDebugLoc();
1201
1202  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1203         "Unexpected instr type to insert");
1204
1205  // To "insert" a SELECT instruction, we actually have to insert the diamond
1206  // control-flow pattern.  The incoming instruction knows the destination vreg
1207  // to set, the condition code register to branch on, the true/false values to
1208  // select between, and a branch opcode to use.
1209  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1210  MachineFunction::iterator I = BB;
1211  ++I;
1212
1213  //  thisMBB:
1214  //  ...
1215  //   TrueVal = ...
1216  //   cmpTY ccX, r1, r2
1217  //   jCC copy1MBB
1218  //   fallthrough --> copy0MBB
1219  MachineBasicBlock *thisMBB = BB;
1220  MachineFunction *F = BB->getParent();
1221  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1222  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1223  F->insert(I, copy0MBB);
1224  F->insert(I, copy1MBB);
1225  // Update machine-CFG edges by transferring all successors of the current
1226  // block to the new block which will contain the Phi node for the select.
1227  copy1MBB->splice(copy1MBB->begin(), BB,
1228                   llvm::next(MachineBasicBlock::iterator(MI)),
1229                   BB->end());
1230  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1231  // Next, add the true and fallthrough blocks as its successors.
1232  BB->addSuccessor(copy0MBB);
1233  BB->addSuccessor(copy1MBB);
1234
1235  BuildMI(BB, dl, TII.get(MSP430::JCC))
1236    .addMBB(copy1MBB)
1237    .addImm(MI->getOperand(3).getImm());
1238
1239  //  copy0MBB:
1240  //   %FalseValue = ...
1241  //   # fallthrough to copy1MBB
1242  BB = copy0MBB;
1243
1244  // Update machine-CFG edges
1245  BB->addSuccessor(copy1MBB);
1246
1247  //  copy1MBB:
1248  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1249  //  ...
1250  BB = copy1MBB;
1251  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1252          MI->getOperand(0).getReg())
1253    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1254    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1255
1256  MI->eraseFromParent();   // The pseudo instruction is gone now.
1257  return BB;
1258}
1259