MSP430ISelLowering.cpp revision 3741be39f98795a841a4d8c35bf54928769ac3cd 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430TargetMachine.h"
19#include "MSP430Subtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/ADT/VectorExtras.h"
39using namespace llvm;
40
41MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
42  TargetLowering(tm, new TargetLoweringObjectFileELF()),
43  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
44
45  // Set up the register classes.
46  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
47  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
48
49  // Compute derived properties from the register classes
50  computeRegisterProperties();
51
52  // Provide all sorts of operation actions
53
54  // Division is expensive
55  setIntDivIsCheap(false);
56
57  // Even if we have only 1 bit shift here, we can perform
58  // shifts of the whole bitwidth 1 bit per step.
59  setShiftAmountType(MVT::i8);
60
61  setStackPointerRegisterToSaveRestore(MSP430::SPW);
62  setBooleanContents(ZeroOrOneBooleanContent);
63  setSchedulingPreference(SchedulingForLatency);
64
65  // We have post-incremented loads / stores.
66  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
67  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
68
69  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
70  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
71  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
72  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
73  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
74
75  // We don't have any truncstores
76  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
77
78  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
79  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
80  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
81  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
82  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
83  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
84  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
85  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
86  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
87  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
88  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
89  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
90  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
91  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
92  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
93  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
94  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
95  setOperationAction(ISD::SETCC,            MVT::i8,    Expand);
96  setOperationAction(ISD::SETCC,            MVT::i16,   Expand);
97  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
98  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
99  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
100  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
101  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
102  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
103  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
104
105  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
106  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
107  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
108  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
109  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
110  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
111
112  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
113  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
114  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
115  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
116  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
117  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
118
119  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
120
121  // FIXME: Implement efficiently multiplication by a constant
122  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
123  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
124  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
125  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
126  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
127  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
128  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
129  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
130  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
131  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
132
133  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
134  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
135  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
136  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
137  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
138  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
139  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
140  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
141  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
142  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
143  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
144  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
145}
146
147SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
148  switch (Op.getOpcode()) {
149  case ISD::SHL: // FALLTHROUGH
150  case ISD::SRL:
151  case ISD::SRA:              return LowerShifts(Op, DAG);
152  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
153  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
154  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
155  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
156  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
157  default:
158    llvm_unreachable("unimplemented operand");
159    return SDValue();
160  }
161}
162
163/// getFunctionAlignment - Return the Log2 alignment of this function.
164unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
165  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
166}
167
168//===----------------------------------------------------------------------===//
169//                       MSP430 Inline Assembly Support
170//===----------------------------------------------------------------------===//
171
172/// getConstraintType - Given a constraint letter, return the type of
173/// constraint it is for this target.
174TargetLowering::ConstraintType
175MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
176  if (Constraint.size() == 1) {
177    switch (Constraint[0]) {
178    case 'r':
179      return C_RegisterClass;
180    default:
181      break;
182    }
183  }
184  return TargetLowering::getConstraintType(Constraint);
185}
186
187std::pair<unsigned, const TargetRegisterClass*>
188MSP430TargetLowering::
189getRegForInlineAsmConstraint(const std::string &Constraint,
190                             EVT VT) const {
191  if (Constraint.size() == 1) {
192    // GCC Constraint Letters
193    switch (Constraint[0]) {
194    default: break;
195    case 'r':   // GENERAL_REGS
196      if (VT == MVT::i8)
197        return std::make_pair(0U, MSP430::GR8RegisterClass);
198
199      return std::make_pair(0U, MSP430::GR16RegisterClass);
200    }
201  }
202
203  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
204}
205
206//===----------------------------------------------------------------------===//
207//                      Calling Convention Implementation
208//===----------------------------------------------------------------------===//
209
210#include "MSP430GenCallingConv.inc"
211
212SDValue
213MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
214                                           CallingConv::ID CallConv,
215                                           bool isVarArg,
216                                           const SmallVectorImpl<ISD::InputArg>
217                                             &Ins,
218                                           DebugLoc dl,
219                                           SelectionDAG &DAG,
220                                           SmallVectorImpl<SDValue> &InVals) {
221
222  switch (CallConv) {
223  default:
224    llvm_unreachable("Unsupported calling convention");
225  case CallingConv::C:
226  case CallingConv::Fast:
227    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
228  }
229}
230
231SDValue
232MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
233                                CallingConv::ID CallConv, bool isVarArg,
234                                bool isTailCall,
235                                const SmallVectorImpl<ISD::OutputArg> &Outs,
236                                const SmallVectorImpl<ISD::InputArg> &Ins,
237                                DebugLoc dl, SelectionDAG &DAG,
238                                SmallVectorImpl<SDValue> &InVals) {
239
240  switch (CallConv) {
241  default:
242    llvm_unreachable("Unsupported calling convention");
243  case CallingConv::Fast:
244  case CallingConv::C:
245    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
246                          Outs, Ins, dl, DAG, InVals);
247  }
248}
249
250/// LowerCCCArguments - transform physical registers into virtual registers and
251/// generate load operations for arguments places on the stack.
252// FIXME: struct return stuff
253// FIXME: varargs
254SDValue
255MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
256                                        CallingConv::ID CallConv,
257                                        bool isVarArg,
258                                        const SmallVectorImpl<ISD::InputArg>
259                                          &Ins,
260                                        DebugLoc dl,
261                                        SelectionDAG &DAG,
262                                        SmallVectorImpl<SDValue> &InVals) {
263  MachineFunction &MF = DAG.getMachineFunction();
264  MachineFrameInfo *MFI = MF.getFrameInfo();
265  MachineRegisterInfo &RegInfo = MF.getRegInfo();
266
267  // Assign locations to all of the incoming arguments.
268  SmallVector<CCValAssign, 16> ArgLocs;
269  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
270                 ArgLocs, *DAG.getContext());
271  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
272
273  assert(!isVarArg && "Varargs not supported yet");
274
275  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
276    CCValAssign &VA = ArgLocs[i];
277    if (VA.isRegLoc()) {
278      // Arguments passed in registers
279      EVT RegVT = VA.getLocVT();
280      switch (RegVT.getSimpleVT().SimpleTy) {
281      default:
282        {
283#ifndef NDEBUG
284          errs() << "LowerFormalArguments Unhandled argument type: "
285               << RegVT.getSimpleVT().SimpleTy << "\n";
286#endif
287          llvm_unreachable(0);
288        }
289      case MVT::i16:
290        unsigned VReg =
291          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
292        RegInfo.addLiveIn(VA.getLocReg(), VReg);
293        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
294
295        // If this is an 8-bit value, it is really passed promoted to 16
296        // bits. Insert an assert[sz]ext to capture this, then truncate to the
297        // right size.
298        if (VA.getLocInfo() == CCValAssign::SExt)
299          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
300                                 DAG.getValueType(VA.getValVT()));
301        else if (VA.getLocInfo() == CCValAssign::ZExt)
302          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
303                                 DAG.getValueType(VA.getValVT()));
304
305        if (VA.getLocInfo() != CCValAssign::Full)
306          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
307
308        InVals.push_back(ArgValue);
309      }
310    } else {
311      // Sanity check
312      assert(VA.isMemLoc());
313      // Load the argument to a virtual register
314      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
315      if (ObjSize > 2) {
316        errs() << "LowerFormalArguments Unhandled argument type: "
317             << VA.getLocVT().getSimpleVT().SimpleTy
318             << "\n";
319      }
320      // Create the frame index object for this incoming parameter...
321      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
322
323      // Create the SelectionDAG nodes corresponding to a load
324      //from this parameter
325      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
326      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
327                                   PseudoSourceValue::getFixedStack(FI), 0));
328    }
329  }
330
331  return Chain;
332}
333
334SDValue
335MSP430TargetLowering::LowerReturn(SDValue Chain,
336                                  CallingConv::ID CallConv, bool isVarArg,
337                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
338                                  DebugLoc dl, SelectionDAG &DAG) {
339
340  // CCValAssign - represent the assignment of the return value to a location
341  SmallVector<CCValAssign, 16> RVLocs;
342
343  // CCState - Info about the registers and stack slot.
344  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
345                 RVLocs, *DAG.getContext());
346
347  // Analize return values.
348  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
349
350  // If this is the first return lowered for this function, add the regs to the
351  // liveout set for the function.
352  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
353    for (unsigned i = 0; i != RVLocs.size(); ++i)
354      if (RVLocs[i].isRegLoc())
355        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
356  }
357
358  SDValue Flag;
359
360  // Copy the result values into the output registers.
361  for (unsigned i = 0; i != RVLocs.size(); ++i) {
362    CCValAssign &VA = RVLocs[i];
363    assert(VA.isRegLoc() && "Can only return in registers!");
364
365    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
366                             Outs[i].Val, Flag);
367
368    // Guarantee that all emitted copies are stuck together,
369    // avoiding something bad.
370    Flag = Chain.getValue(1);
371  }
372
373  if (Flag.getNode())
374    return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
375
376  // Return Void
377  return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
378}
379
380/// LowerCCCCallTo - functions arguments are copied from virtual regs to
381/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
382/// TODO: sret.
383SDValue
384MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
385                                     CallingConv::ID CallConv, bool isVarArg,
386                                     bool isTailCall,
387                                     const SmallVectorImpl<ISD::OutputArg>
388                                       &Outs,
389                                     const SmallVectorImpl<ISD::InputArg> &Ins,
390                                     DebugLoc dl, SelectionDAG &DAG,
391                                     SmallVectorImpl<SDValue> &InVals) {
392  // Analyze operands of the call, assigning locations to each operand.
393  SmallVector<CCValAssign, 16> ArgLocs;
394  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
395                 ArgLocs, *DAG.getContext());
396
397  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
398
399  // Get a count of how many bytes are to be pushed on the stack.
400  unsigned NumBytes = CCInfo.getNextStackOffset();
401
402  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
403                                                      getPointerTy(), true));
404
405  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
406  SmallVector<SDValue, 12> MemOpChains;
407  SDValue StackPtr;
408
409  // Walk the register/memloc assignments, inserting copies/loads.
410  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
411    CCValAssign &VA = ArgLocs[i];
412
413    SDValue Arg = Outs[i].Val;
414
415    // Promote the value if needed.
416    switch (VA.getLocInfo()) {
417      default: llvm_unreachable("Unknown loc info!");
418      case CCValAssign::Full: break;
419      case CCValAssign::SExt:
420        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
421        break;
422      case CCValAssign::ZExt:
423        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
424        break;
425      case CCValAssign::AExt:
426        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
427        break;
428    }
429
430    // Arguments that can be passed on register must be kept at RegsToPass
431    // vector
432    if (VA.isRegLoc()) {
433      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
434    } else {
435      assert(VA.isMemLoc());
436
437      if (StackPtr.getNode() == 0)
438        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
439
440      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
441                                   StackPtr,
442                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
443
444
445      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
446                                         PseudoSourceValue::getStack(),
447                                         VA.getLocMemOffset()));
448    }
449  }
450
451  // Transform all store nodes into one single node because all store nodes are
452  // independent of each other.
453  if (!MemOpChains.empty())
454    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
455                        &MemOpChains[0], MemOpChains.size());
456
457  // Build a sequence of copy-to-reg nodes chained together with token chain and
458  // flag operands which copy the outgoing args into registers.  The InFlag in
459  // necessary since all emited instructions must be stuck together.
460  SDValue InFlag;
461  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
462    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
463                             RegsToPass[i].second, InFlag);
464    InFlag = Chain.getValue(1);
465  }
466
467  // If the callee is a GlobalAddress node (quite common, every direct call is)
468  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
469  // Likewise ExternalSymbol -> TargetExternalSymbol.
470  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
471    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
472  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
473    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
474
475  // Returns a chain & a flag for retval copy to use.
476  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
477  SmallVector<SDValue, 8> Ops;
478  Ops.push_back(Chain);
479  Ops.push_back(Callee);
480
481  // Add argument registers to the end of the list so that they are
482  // known live into the call.
483  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
484    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
485                                  RegsToPass[i].second.getValueType()));
486
487  if (InFlag.getNode())
488    Ops.push_back(InFlag);
489
490  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
491  InFlag = Chain.getValue(1);
492
493  // Create the CALLSEQ_END node.
494  Chain = DAG.getCALLSEQ_END(Chain,
495                             DAG.getConstant(NumBytes, getPointerTy(), true),
496                             DAG.getConstant(0, getPointerTy(), true),
497                             InFlag);
498  InFlag = Chain.getValue(1);
499
500  // Handle result values, copying them out of physregs into vregs that we
501  // return.
502  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
503                         DAG, InVals);
504}
505
506/// LowerCallResult - Lower the result values of a call into the
507/// appropriate copies out of appropriate physical registers.
508///
509SDValue
510MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
511                                      CallingConv::ID CallConv, bool isVarArg,
512                                      const SmallVectorImpl<ISD::InputArg> &Ins,
513                                      DebugLoc dl, SelectionDAG &DAG,
514                                      SmallVectorImpl<SDValue> &InVals) {
515
516  // Assign locations to each value returned by this call.
517  SmallVector<CCValAssign, 16> RVLocs;
518  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
519                 RVLocs, *DAG.getContext());
520
521  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
522
523  // Copy all of the result registers out of their specified physreg.
524  for (unsigned i = 0; i != RVLocs.size(); ++i) {
525    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
526                               RVLocs[i].getValVT(), InFlag).getValue(1);
527    InFlag = Chain.getValue(2);
528    InVals.push_back(Chain.getValue(0));
529  }
530
531  return Chain;
532}
533
534SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
535                                          SelectionDAG &DAG) {
536  unsigned Opc = Op.getOpcode();
537  SDNode* N = Op.getNode();
538  EVT VT = Op.getValueType();
539  DebugLoc dl = N->getDebugLoc();
540
541  // We currently only lower shifts of constant argument.
542  if (!isa<ConstantSDNode>(N->getOperand(1)))
543    return SDValue();
544
545  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
546
547  // Expand the stuff into sequence of shifts.
548  // FIXME: for some shift amounts this might be done better!
549  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
550  SDValue Victim = N->getOperand(0);
551
552  if (Opc == ISD::SRL && ShiftAmount) {
553    // Emit a special goodness here:
554    // srl A, 1 => clrc; rrc A
555    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
556    ShiftAmount -= 1;
557  }
558
559  while (ShiftAmount--)
560    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
561                         dl, VT, Victim);
562
563  return Victim;
564}
565
566SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
567  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
568  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
569
570  // Create the TargetGlobalAddress node, folding in the constant offset.
571  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
572  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
573                     getPointerTy(), Result);
574}
575
576SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
577                                                  SelectionDAG &DAG) {
578  DebugLoc dl = Op.getDebugLoc();
579  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
580  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
581
582  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
583}
584
585static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
586                       ISD::CondCode CC,
587                       DebugLoc dl, SelectionDAG &DAG) {
588  // FIXME: Handle bittests someday
589  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
590
591  // FIXME: Handle jump negative someday
592  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
593  switch (CC) {
594  default: llvm_unreachable("Invalid integer condition!");
595  case ISD::SETEQ:
596    TCC = MSP430CC::COND_E;     // aka COND_Z
597    break;
598  case ISD::SETNE:
599    TCC = MSP430CC::COND_NE;    // aka COND_NZ
600    break;
601  case ISD::SETULE:
602    std::swap(LHS, RHS);        // FALLTHROUGH
603  case ISD::SETUGE:
604    TCC = MSP430CC::COND_HS;    // aka COND_C
605    break;
606  case ISD::SETUGT:
607    std::swap(LHS, RHS);        // FALLTHROUGH
608  case ISD::SETULT:
609    TCC = MSP430CC::COND_LO;    // aka COND_NC
610    break;
611  case ISD::SETLE:
612    std::swap(LHS, RHS);        // FALLTHROUGH
613  case ISD::SETGE:
614    TCC = MSP430CC::COND_GE;
615    break;
616  case ISD::SETGT:
617    std::swap(LHS, RHS);        // FALLTHROUGH
618  case ISD::SETLT:
619    TCC = MSP430CC::COND_L;
620    break;
621  }
622
623  TargetCC = DAG.getConstant(TCC, MVT::i8);
624  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
625}
626
627
628SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
629  SDValue Chain = Op.getOperand(0);
630  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
631  SDValue LHS   = Op.getOperand(2);
632  SDValue RHS   = Op.getOperand(3);
633  SDValue Dest  = Op.getOperand(4);
634  DebugLoc dl   = Op.getDebugLoc();
635
636  SDValue TargetCC;
637  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
638
639  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
640                     Chain, Dest, TargetCC, Flag);
641}
642
643SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
644  SDValue LHS    = Op.getOperand(0);
645  SDValue RHS    = Op.getOperand(1);
646  SDValue TrueV  = Op.getOperand(2);
647  SDValue FalseV = Op.getOperand(3);
648  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
649  DebugLoc dl    = Op.getDebugLoc();
650
651  SDValue TargetCC;
652  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
653
654  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
655  SmallVector<SDValue, 4> Ops;
656  Ops.push_back(TrueV);
657  Ops.push_back(FalseV);
658  Ops.push_back(TargetCC);
659  Ops.push_back(Flag);
660
661  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
662}
663
664SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
665                                               SelectionDAG &DAG) {
666  SDValue Val = Op.getOperand(0);
667  EVT VT      = Op.getValueType();
668  DebugLoc dl = Op.getDebugLoc();
669
670  assert(VT == MVT::i16 && "Only support i16 for now!");
671
672  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
673                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
674                     DAG.getValueType(Val.getValueType()));
675}
676
677/// getPostIndexedAddressParts - returns true by value, base pointer and
678/// offset pointer and addressing mode by reference if this node can be
679/// combined with a load / store to form a post-indexed load / store.
680bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
681                                                      SDValue &Base,
682                                                      SDValue &Offset,
683                                                      ISD::MemIndexedMode &AM,
684                                                      SelectionDAG &DAG) const {
685
686  LoadSDNode *LD = cast<LoadSDNode>(N);
687  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
688    return false;
689
690  EVT VT = LD->getMemoryVT();
691  if (VT != MVT::i8 && VT != MVT::i16)
692    return false;
693
694  if (Op->getOpcode() != ISD::ADD)
695    return false;
696
697  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
698    uint64_t RHSC = RHS->getZExtValue();
699    if ((VT == MVT::i16 && RHSC != 2) ||
700        (VT == MVT::i8 && RHSC != 1))
701      return false;
702
703    Base = Op->getOperand(0);
704    Offset = DAG.getConstant(RHSC, VT);
705    AM = ISD::POST_INC;
706    return true;
707  }
708
709  return false;
710}
711
712
713const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
714  switch (Opcode) {
715  default: return NULL;
716  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
717  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
718  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
719  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
720  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
721  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
722  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
723  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
724  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
725  }
726}
727
728//===----------------------------------------------------------------------===//
729//  Other Lowering Code
730//===----------------------------------------------------------------------===//
731
732MachineBasicBlock*
733MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
734                                                  MachineBasicBlock *BB,
735                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
736  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
737  DebugLoc dl = MI->getDebugLoc();
738  assert((MI->getOpcode() == MSP430::Select16 ||
739          MI->getOpcode() == MSP430::Select8) &&
740         "Unexpected instr type to insert");
741
742  // To "insert" a SELECT instruction, we actually have to insert the diamond
743  // control-flow pattern.  The incoming instruction knows the destination vreg
744  // to set, the condition code register to branch on, the true/false values to
745  // select between, and a branch opcode to use.
746  const BasicBlock *LLVM_BB = BB->getBasicBlock();
747  MachineFunction::iterator I = BB;
748  ++I;
749
750  //  thisMBB:
751  //  ...
752  //   TrueVal = ...
753  //   cmpTY ccX, r1, r2
754  //   jCC copy1MBB
755  //   fallthrough --> copy0MBB
756  MachineBasicBlock *thisMBB = BB;
757  MachineFunction *F = BB->getParent();
758  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
759  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
760  BuildMI(BB, dl, TII.get(MSP430::JCC))
761    .addMBB(copy1MBB)
762    .addImm(MI->getOperand(3).getImm());
763  F->insert(I, copy0MBB);
764  F->insert(I, copy1MBB);
765  // Inform sdisel of the edge changes.
766  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
767         SE = BB->succ_end(); SI != SE; ++SI)
768    EM->insert(std::make_pair(*SI, copy1MBB));
769  // Update machine-CFG edges by transferring all successors of the current
770  // block to the new block which will contain the Phi node for the select.
771  copy1MBB->transferSuccessors(BB);
772  // Next, add the true and fallthrough blocks as its successors.
773  BB->addSuccessor(copy0MBB);
774  BB->addSuccessor(copy1MBB);
775
776  //  copy0MBB:
777  //   %FalseValue = ...
778  //   # fallthrough to copy1MBB
779  BB = copy0MBB;
780
781  // Update machine-CFG edges
782  BB->addSuccessor(copy1MBB);
783
784  //  copy1MBB:
785  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
786  //  ...
787  BB = copy1MBB;
788  BuildMI(BB, dl, TII.get(MSP430::PHI),
789          MI->getOperand(0).getReg())
790    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
791    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
792
793  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
794  return BB;
795}
796