MSP430ISelLowering.cpp revision 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41typedef enum {
42  NoHWMult,
43  HWMultIntr,
44  HWMultNoIntr
45} HWMultUseMode;
46
47static cl::opt<HWMultUseMode>
48HWMultMode("msp430-hwmult-mode",
49           cl::desc("Hardware multiplier use mode"),
50           cl::init(HWMultNoIntr),
51           cl::values(
52             clEnumValN(NoHWMult, "no",
53                "Do not use hardware multiplier"),
54             clEnumValN(HWMultIntr, "interrupts",
55                "Assume hardware multiplier can be used inside interrupts"),
56             clEnumValN(HWMultNoIntr, "use",
57                "Assume hardware multiplier cannot be used inside interrupts"),
58             clEnumValEnd));
59
60MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
61  TargetLowering(tm, new TargetLoweringObjectFileELF()),
62  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
63
64  TD = getTargetData();
65
66  // Set up the register classes.
67  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
68  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
69
70  // Compute derived properties from the register classes
71  computeRegisterProperties();
72
73  // Provide all sorts of operation actions
74
75  // Division is expensive
76  setIntDivIsCheap(false);
77
78  setStackPointerRegisterToSaveRestore(MSP430::SPW);
79  setBooleanContents(ZeroOrOneBooleanContent);
80  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
81
82  // We have post-incremented loads / stores.
83  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
85
86  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
88  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
89  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
90  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
91
92  // We don't have any truncstores
93  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
96  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
97  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
98  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
99  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
100  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
101  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
102  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
103  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
104  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
105  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
106  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
107  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
108  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
110  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
111  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
112  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
113  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
114  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
115  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
116  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
117  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
118  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
119  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
123  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
124  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i8,    Expand);
125  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i16,   Expand);
126  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
128  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i8,    Expand);
129  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i16,   Expand);
130  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
131  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
132
133  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
134  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
135  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
139
140  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
141
142  // FIXME: Implement efficiently multiplication by a constant
143  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
144  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
145  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
146  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
147  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
148  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
149  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
150  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
151  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
152  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
153
154  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
155  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
156  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
157  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
158  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
159  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
160  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
161  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
162  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
163  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
164  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
165  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
166
167  // Libcalls names.
168  if (HWMultMode == HWMultIntr) {
169    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
170    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
171  } else if (HWMultMode == HWMultNoIntr) {
172    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
173    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
174  }
175
176  setMinFunctionAlignment(1);
177  setPrefFunctionAlignment(2);
178}
179
180SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
181                                             SelectionDAG &DAG) const {
182  switch (Op.getOpcode()) {
183  case ISD::SHL: // FALLTHROUGH
184  case ISD::SRL:
185  case ISD::SRA:              return LowerShifts(Op, DAG);
186  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
187  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
188  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
189  case ISD::SETCC:            return LowerSETCC(Op, DAG);
190  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
191  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
192  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
193  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
194  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
195  default:
196    llvm_unreachable("unimplemented operand");
197  }
198}
199
200//===----------------------------------------------------------------------===//
201//                       MSP430 Inline Assembly Support
202//===----------------------------------------------------------------------===//
203
204/// getConstraintType - Given a constraint letter, return the type of
205/// constraint it is for this target.
206TargetLowering::ConstraintType
207MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
208  if (Constraint.size() == 1) {
209    switch (Constraint[0]) {
210    case 'r':
211      return C_RegisterClass;
212    default:
213      break;
214    }
215  }
216  return TargetLowering::getConstraintType(Constraint);
217}
218
219std::pair<unsigned, const TargetRegisterClass*>
220MSP430TargetLowering::
221getRegForInlineAsmConstraint(const std::string &Constraint,
222                             EVT VT) const {
223  if (Constraint.size() == 1) {
224    // GCC Constraint Letters
225    switch (Constraint[0]) {
226    default: break;
227    case 'r':   // GENERAL_REGS
228      if (VT == MVT::i8)
229        return std::make_pair(0U, MSP430::GR8RegisterClass);
230
231      return std::make_pair(0U, MSP430::GR16RegisterClass);
232    }
233  }
234
235  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
236}
237
238//===----------------------------------------------------------------------===//
239//                      Calling Convention Implementation
240//===----------------------------------------------------------------------===//
241
242#include "MSP430GenCallingConv.inc"
243
244SDValue
245MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
246                                           CallingConv::ID CallConv,
247                                           bool isVarArg,
248                                           const SmallVectorImpl<ISD::InputArg>
249                                             &Ins,
250                                           DebugLoc dl,
251                                           SelectionDAG &DAG,
252                                           SmallVectorImpl<SDValue> &InVals)
253                                             const {
254
255  switch (CallConv) {
256  default:
257    llvm_unreachable("Unsupported calling convention");
258  case CallingConv::C:
259  case CallingConv::Fast:
260    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
261  case CallingConv::MSP430_INTR:
262    if (Ins.empty())
263      return Chain;
264    report_fatal_error("ISRs cannot have arguments");
265  }
266}
267
268SDValue
269MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
270                                CallingConv::ID CallConv, bool isVarArg,
271                                bool &isTailCall,
272                                const SmallVectorImpl<ISD::OutputArg> &Outs,
273                                const SmallVectorImpl<SDValue> &OutVals,
274                                const SmallVectorImpl<ISD::InputArg> &Ins,
275                                DebugLoc dl, SelectionDAG &DAG,
276                                SmallVectorImpl<SDValue> &InVals) const {
277  // MSP430 target does not yet support tail call optimization.
278  isTailCall = false;
279
280  switch (CallConv) {
281  default:
282    llvm_unreachable("Unsupported calling convention");
283  case CallingConv::Fast:
284  case CallingConv::C:
285    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
286                          Outs, OutVals, Ins, dl, DAG, InVals);
287  case CallingConv::MSP430_INTR:
288    report_fatal_error("ISRs cannot be called directly");
289  }
290}
291
292/// LowerCCCArguments - transform physical registers into virtual registers and
293/// generate load operations for arguments places on the stack.
294// FIXME: struct return stuff
295// FIXME: varargs
296SDValue
297MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
298                                        CallingConv::ID CallConv,
299                                        bool isVarArg,
300                                        const SmallVectorImpl<ISD::InputArg>
301                                          &Ins,
302                                        DebugLoc dl,
303                                        SelectionDAG &DAG,
304                                        SmallVectorImpl<SDValue> &InVals)
305                                          const {
306  MachineFunction &MF = DAG.getMachineFunction();
307  MachineFrameInfo *MFI = MF.getFrameInfo();
308  MachineRegisterInfo &RegInfo = MF.getRegInfo();
309
310  // Assign locations to all of the incoming arguments.
311  SmallVector<CCValAssign, 16> ArgLocs;
312  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
313		 getTargetMachine(), ArgLocs, *DAG.getContext());
314  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
315
316  assert(!isVarArg && "Varargs not supported yet");
317
318  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
319    CCValAssign &VA = ArgLocs[i];
320    if (VA.isRegLoc()) {
321      // Arguments passed in registers
322      EVT RegVT = VA.getLocVT();
323      switch (RegVT.getSimpleVT().SimpleTy) {
324      default:
325        {
326#ifndef NDEBUG
327          errs() << "LowerFormalArguments Unhandled argument type: "
328               << RegVT.getSimpleVT().SimpleTy << "\n";
329#endif
330          llvm_unreachable(0);
331        }
332      case MVT::i16:
333        unsigned VReg =
334          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
335        RegInfo.addLiveIn(VA.getLocReg(), VReg);
336        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
337
338        // If this is an 8-bit value, it is really passed promoted to 16
339        // bits. Insert an assert[sz]ext to capture this, then truncate to the
340        // right size.
341        if (VA.getLocInfo() == CCValAssign::SExt)
342          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
343                                 DAG.getValueType(VA.getValVT()));
344        else if (VA.getLocInfo() == CCValAssign::ZExt)
345          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
346                                 DAG.getValueType(VA.getValVT()));
347
348        if (VA.getLocInfo() != CCValAssign::Full)
349          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
350
351        InVals.push_back(ArgValue);
352      }
353    } else {
354      // Sanity check
355      assert(VA.isMemLoc());
356      // Load the argument to a virtual register
357      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
358      if (ObjSize > 2) {
359        errs() << "LowerFormalArguments Unhandled argument type: "
360             << EVT(VA.getLocVT()).getEVTString()
361             << "\n";
362      }
363      // Create the frame index object for this incoming parameter...
364      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
365
366      // Create the SelectionDAG nodes corresponding to a load
367      //from this parameter
368      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
369      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
370                                   MachinePointerInfo::getFixedStack(FI),
371                                   false, false, false, 0));
372    }
373  }
374
375  return Chain;
376}
377
378SDValue
379MSP430TargetLowering::LowerReturn(SDValue Chain,
380                                  CallingConv::ID CallConv, bool isVarArg,
381                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
382                                  const SmallVectorImpl<SDValue> &OutVals,
383                                  DebugLoc dl, SelectionDAG &DAG) const {
384
385  // CCValAssign - represent the assignment of the return value to a location
386  SmallVector<CCValAssign, 16> RVLocs;
387
388  // ISRs cannot return any value.
389  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
390    report_fatal_error("ISRs cannot return any value");
391
392  // CCState - Info about the registers and stack slot.
393  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
394		 getTargetMachine(), RVLocs, *DAG.getContext());
395
396  // Analize return values.
397  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
398
399  // If this is the first return lowered for this function, add the regs to the
400  // liveout set for the function.
401  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
402    for (unsigned i = 0; i != RVLocs.size(); ++i)
403      if (RVLocs[i].isRegLoc())
404        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
405  }
406
407  SDValue Flag;
408
409  // Copy the result values into the output registers.
410  for (unsigned i = 0; i != RVLocs.size(); ++i) {
411    CCValAssign &VA = RVLocs[i];
412    assert(VA.isRegLoc() && "Can only return in registers!");
413
414    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
415                             OutVals[i], Flag);
416
417    // Guarantee that all emitted copies are stuck together,
418    // avoiding something bad.
419    Flag = Chain.getValue(1);
420  }
421
422  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
423                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
424
425  if (Flag.getNode())
426    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
427
428  // Return Void
429  return DAG.getNode(Opc, dl, MVT::Other, Chain);
430}
431
432/// LowerCCCCallTo - functions arguments are copied from virtual regs to
433/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
434/// TODO: sret.
435SDValue
436MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
437                                     CallingConv::ID CallConv, bool isVarArg,
438                                     bool isTailCall,
439                                     const SmallVectorImpl<ISD::OutputArg>
440                                       &Outs,
441                                     const SmallVectorImpl<SDValue> &OutVals,
442                                     const SmallVectorImpl<ISD::InputArg> &Ins,
443                                     DebugLoc dl, SelectionDAG &DAG,
444                                     SmallVectorImpl<SDValue> &InVals) const {
445  // Analyze operands of the call, assigning locations to each operand.
446  SmallVector<CCValAssign, 16> ArgLocs;
447  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
448		 getTargetMachine(), ArgLocs, *DAG.getContext());
449
450  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
451
452  // Get a count of how many bytes are to be pushed on the stack.
453  unsigned NumBytes = CCInfo.getNextStackOffset();
454
455  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
456                                                      getPointerTy(), true));
457
458  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
459  SmallVector<SDValue, 12> MemOpChains;
460  SDValue StackPtr;
461
462  // Walk the register/memloc assignments, inserting copies/loads.
463  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
464    CCValAssign &VA = ArgLocs[i];
465
466    SDValue Arg = OutVals[i];
467
468    // Promote the value if needed.
469    switch (VA.getLocInfo()) {
470      default: llvm_unreachable("Unknown loc info!");
471      case CCValAssign::Full: break;
472      case CCValAssign::SExt:
473        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
474        break;
475      case CCValAssign::ZExt:
476        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
477        break;
478      case CCValAssign::AExt:
479        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
480        break;
481    }
482
483    // Arguments that can be passed on register must be kept at RegsToPass
484    // vector
485    if (VA.isRegLoc()) {
486      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
487    } else {
488      assert(VA.isMemLoc());
489
490      if (StackPtr.getNode() == 0)
491        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
492
493      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
494                                   StackPtr,
495                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
496
497
498      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
499                                         MachinePointerInfo(),false, false, 0));
500    }
501  }
502
503  // Transform all store nodes into one single node because all store nodes are
504  // independent of each other.
505  if (!MemOpChains.empty())
506    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
507                        &MemOpChains[0], MemOpChains.size());
508
509  // Build a sequence of copy-to-reg nodes chained together with token chain and
510  // flag operands which copy the outgoing args into registers.  The InFlag in
511  // necessary since all emitted instructions must be stuck together.
512  SDValue InFlag;
513  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
514    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
515                             RegsToPass[i].second, InFlag);
516    InFlag = Chain.getValue(1);
517  }
518
519  // If the callee is a GlobalAddress node (quite common, every direct call is)
520  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
521  // Likewise ExternalSymbol -> TargetExternalSymbol.
522  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
523    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
524  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
525    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
526
527  // Returns a chain & a flag for retval copy to use.
528  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
529  SmallVector<SDValue, 8> Ops;
530  Ops.push_back(Chain);
531  Ops.push_back(Callee);
532
533  // Add argument registers to the end of the list so that they are
534  // known live into the call.
535  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
536    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
537                                  RegsToPass[i].second.getValueType()));
538
539  if (InFlag.getNode())
540    Ops.push_back(InFlag);
541
542  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
543  InFlag = Chain.getValue(1);
544
545  // Create the CALLSEQ_END node.
546  Chain = DAG.getCALLSEQ_END(Chain,
547                             DAG.getConstant(NumBytes, getPointerTy(), true),
548                             DAG.getConstant(0, getPointerTy(), true),
549                             InFlag);
550  InFlag = Chain.getValue(1);
551
552  // Handle result values, copying them out of physregs into vregs that we
553  // return.
554  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
555                         DAG, InVals);
556}
557
558/// LowerCallResult - Lower the result values of a call into the
559/// appropriate copies out of appropriate physical registers.
560///
561SDValue
562MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
563                                      CallingConv::ID CallConv, bool isVarArg,
564                                      const SmallVectorImpl<ISD::InputArg> &Ins,
565                                      DebugLoc dl, SelectionDAG &DAG,
566                                      SmallVectorImpl<SDValue> &InVals) const {
567
568  // Assign locations to each value returned by this call.
569  SmallVector<CCValAssign, 16> RVLocs;
570  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
571		 getTargetMachine(), RVLocs, *DAG.getContext());
572
573  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
574
575  // Copy all of the result registers out of their specified physreg.
576  for (unsigned i = 0; i != RVLocs.size(); ++i) {
577    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
578                               RVLocs[i].getValVT(), InFlag).getValue(1);
579    InFlag = Chain.getValue(2);
580    InVals.push_back(Chain.getValue(0));
581  }
582
583  return Chain;
584}
585
586SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
587                                          SelectionDAG &DAG) const {
588  unsigned Opc = Op.getOpcode();
589  SDNode* N = Op.getNode();
590  EVT VT = Op.getValueType();
591  DebugLoc dl = N->getDebugLoc();
592
593  // Expand non-constant shifts to loops:
594  if (!isa<ConstantSDNode>(N->getOperand(1)))
595    switch (Opc) {
596    default:
597      assert(0 && "Invalid shift opcode!");
598    case ISD::SHL:
599      return DAG.getNode(MSP430ISD::SHL, dl,
600                         VT, N->getOperand(0), N->getOperand(1));
601    case ISD::SRA:
602      return DAG.getNode(MSP430ISD::SRA, dl,
603                         VT, N->getOperand(0), N->getOperand(1));
604    case ISD::SRL:
605      return DAG.getNode(MSP430ISD::SRL, dl,
606                         VT, N->getOperand(0), N->getOperand(1));
607    }
608
609  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
610
611  // Expand the stuff into sequence of shifts.
612  // FIXME: for some shift amounts this might be done better!
613  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
614  SDValue Victim = N->getOperand(0);
615
616  if (Opc == ISD::SRL && ShiftAmount) {
617    // Emit a special goodness here:
618    // srl A, 1 => clrc; rrc A
619    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
620    ShiftAmount -= 1;
621  }
622
623  while (ShiftAmount--)
624    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
625                         dl, VT, Victim);
626
627  return Victim;
628}
629
630SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
631                                                 SelectionDAG &DAG) const {
632  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
633  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
634
635  // Create the TargetGlobalAddress node, folding in the constant offset.
636  SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
637                                              getPointerTy(), Offset);
638  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
639                     getPointerTy(), Result);
640}
641
642SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
643                                                  SelectionDAG &DAG) const {
644  DebugLoc dl = Op.getDebugLoc();
645  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
646  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
647
648  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
649}
650
651SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
652                                                SelectionDAG &DAG) const {
653  DebugLoc dl = Op.getDebugLoc();
654  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
655  SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
656
657  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
658}
659
660static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
661                       ISD::CondCode CC,
662                       DebugLoc dl, SelectionDAG &DAG) {
663  // FIXME: Handle bittests someday
664  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
665
666  // FIXME: Handle jump negative someday
667  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
668  switch (CC) {
669  default: llvm_unreachable("Invalid integer condition!");
670  case ISD::SETEQ:
671    TCC = MSP430CC::COND_E;     // aka COND_Z
672    // Minor optimization: if LHS is a constant, swap operands, then the
673    // constant can be folded into comparison.
674    if (LHS.getOpcode() == ISD::Constant)
675      std::swap(LHS, RHS);
676    break;
677  case ISD::SETNE:
678    TCC = MSP430CC::COND_NE;    // aka COND_NZ
679    // Minor optimization: if LHS is a constant, swap operands, then the
680    // constant can be folded into comparison.
681    if (LHS.getOpcode() == ISD::Constant)
682      std::swap(LHS, RHS);
683    break;
684  case ISD::SETULE:
685    std::swap(LHS, RHS);        // FALLTHROUGH
686  case ISD::SETUGE:
687    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
688    // fold constant into instruction.
689    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
690      LHS = RHS;
691      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
692      TCC = MSP430CC::COND_LO;
693      break;
694    }
695    TCC = MSP430CC::COND_HS;    // aka COND_C
696    break;
697  case ISD::SETUGT:
698    std::swap(LHS, RHS);        // FALLTHROUGH
699  case ISD::SETULT:
700    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
701    // fold constant into instruction.
702    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
703      LHS = RHS;
704      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
705      TCC = MSP430CC::COND_HS;
706      break;
707    }
708    TCC = MSP430CC::COND_LO;    // aka COND_NC
709    break;
710  case ISD::SETLE:
711    std::swap(LHS, RHS);        // FALLTHROUGH
712  case ISD::SETGE:
713    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
714    // fold constant into instruction.
715    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
716      LHS = RHS;
717      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
718      TCC = MSP430CC::COND_L;
719      break;
720    }
721    TCC = MSP430CC::COND_GE;
722    break;
723  case ISD::SETGT:
724    std::swap(LHS, RHS);        // FALLTHROUGH
725  case ISD::SETLT:
726    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
727    // fold constant into instruction.
728    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
729      LHS = RHS;
730      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
731      TCC = MSP430CC::COND_GE;
732      break;
733    }
734    TCC = MSP430CC::COND_L;
735    break;
736  }
737
738  TargetCC = DAG.getConstant(TCC, MVT::i8);
739  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
740}
741
742
743SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
744  SDValue Chain = Op.getOperand(0);
745  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
746  SDValue LHS   = Op.getOperand(2);
747  SDValue RHS   = Op.getOperand(3);
748  SDValue Dest  = Op.getOperand(4);
749  DebugLoc dl   = Op.getDebugLoc();
750
751  SDValue TargetCC;
752  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
753
754  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
755                     Chain, Dest, TargetCC, Flag);
756}
757
758SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
759  SDValue LHS   = Op.getOperand(0);
760  SDValue RHS   = Op.getOperand(1);
761  DebugLoc dl   = Op.getDebugLoc();
762
763  // If we are doing an AND and testing against zero, then the CMP
764  // will not be generated.  The AND (or BIT) will generate the condition codes,
765  // but they are different from CMP.
766  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
767  // lowering & isel wouldn't diverge.
768  bool andCC = false;
769  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
770    if (RHSC->isNullValue() && LHS.hasOneUse() &&
771        (LHS.getOpcode() == ISD::AND ||
772         (LHS.getOpcode() == ISD::TRUNCATE &&
773          LHS.getOperand(0).getOpcode() == ISD::AND))) {
774      andCC = true;
775    }
776  }
777  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
778  SDValue TargetCC;
779  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
780
781  // Get the condition codes directly from the status register, if its easy.
782  // Otherwise a branch will be generated.  Note that the AND and BIT
783  // instructions generate different flags than CMP, the carry bit can be used
784  // for NE/EQ.
785  bool Invert = false;
786  bool Shift = false;
787  bool Convert = true;
788  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
789   default:
790    Convert = false;
791    break;
792   case MSP430CC::COND_HS:
793     // Res = SRW & 1, no processing is required
794     break;
795   case MSP430CC::COND_LO:
796     // Res = ~(SRW & 1)
797     Invert = true;
798     break;
799   case MSP430CC::COND_NE:
800     if (andCC) {
801       // C = ~Z, thus Res = SRW & 1, no processing is required
802     } else {
803       // Res = ~((SRW >> 1) & 1)
804       Shift = true;
805       Invert = true;
806     }
807     break;
808   case MSP430CC::COND_E:
809     Shift = true;
810     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
811     // Res = (SRW >> 1) & 1 is 1 word shorter.
812     break;
813  }
814  EVT VT = Op.getValueType();
815  SDValue One  = DAG.getConstant(1, VT);
816  if (Convert) {
817    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
818                                    MVT::i16, Flag);
819    if (Shift)
820      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
821      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
822    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
823    if (Invert)
824      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
825    return SR;
826  } else {
827    SDValue Zero = DAG.getConstant(0, VT);
828    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
829    SmallVector<SDValue, 4> Ops;
830    Ops.push_back(One);
831    Ops.push_back(Zero);
832    Ops.push_back(TargetCC);
833    Ops.push_back(Flag);
834    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
835  }
836}
837
838SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
839                                             SelectionDAG &DAG) const {
840  SDValue LHS    = Op.getOperand(0);
841  SDValue RHS    = Op.getOperand(1);
842  SDValue TrueV  = Op.getOperand(2);
843  SDValue FalseV = Op.getOperand(3);
844  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
845  DebugLoc dl    = Op.getDebugLoc();
846
847  SDValue TargetCC;
848  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
849
850  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
851  SmallVector<SDValue, 4> Ops;
852  Ops.push_back(TrueV);
853  Ops.push_back(FalseV);
854  Ops.push_back(TargetCC);
855  Ops.push_back(Flag);
856
857  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
858}
859
860SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
861                                               SelectionDAG &DAG) const {
862  SDValue Val = Op.getOperand(0);
863  EVT VT      = Op.getValueType();
864  DebugLoc dl = Op.getDebugLoc();
865
866  assert(VT == MVT::i16 && "Only support i16 for now!");
867
868  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
869                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
870                     DAG.getValueType(Val.getValueType()));
871}
872
873SDValue
874MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
875  MachineFunction &MF = DAG.getMachineFunction();
876  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
877  int ReturnAddrIndex = FuncInfo->getRAIndex();
878
879  if (ReturnAddrIndex == 0) {
880    // Set up a frame object for the return address.
881    uint64_t SlotSize = TD->getPointerSize();
882    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
883                                                           true);
884    FuncInfo->setRAIndex(ReturnAddrIndex);
885  }
886
887  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
888}
889
890SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
891                                              SelectionDAG &DAG) const {
892  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
893  MFI->setReturnAddressIsTaken(true);
894
895  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
896  DebugLoc dl = Op.getDebugLoc();
897
898  if (Depth > 0) {
899    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
900    SDValue Offset =
901      DAG.getConstant(TD->getPointerSize(), MVT::i16);
902    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
903                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
904                                   FrameAddr, Offset),
905                       MachinePointerInfo(), false, false, false, 0);
906  }
907
908  // Just load the return address.
909  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
910  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
911                     RetAddrFI, MachinePointerInfo(), false, false, false, 0);
912}
913
914SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
915                                             SelectionDAG &DAG) const {
916  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
917  MFI->setFrameAddressIsTaken(true);
918
919  EVT VT = Op.getValueType();
920  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
921  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
922  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
923                                         MSP430::FPW, VT);
924  while (Depth--)
925    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
926                            MachinePointerInfo(),
927                            false, false, false, 0);
928  return FrameAddr;
929}
930
931/// getPostIndexedAddressParts - returns true by value, base pointer and
932/// offset pointer and addressing mode by reference if this node can be
933/// combined with a load / store to form a post-indexed load / store.
934bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
935                                                      SDValue &Base,
936                                                      SDValue &Offset,
937                                                      ISD::MemIndexedMode &AM,
938                                                      SelectionDAG &DAG) const {
939
940  LoadSDNode *LD = cast<LoadSDNode>(N);
941  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
942    return false;
943
944  EVT VT = LD->getMemoryVT();
945  if (VT != MVT::i8 && VT != MVT::i16)
946    return false;
947
948  if (Op->getOpcode() != ISD::ADD)
949    return false;
950
951  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
952    uint64_t RHSC = RHS->getZExtValue();
953    if ((VT == MVT::i16 && RHSC != 2) ||
954        (VT == MVT::i8 && RHSC != 1))
955      return false;
956
957    Base = Op->getOperand(0);
958    Offset = DAG.getConstant(RHSC, VT);
959    AM = ISD::POST_INC;
960    return true;
961  }
962
963  return false;
964}
965
966
967const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
968  switch (Opcode) {
969  default: return NULL;
970  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
971  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
972  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
973  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
974  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
975  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
976  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
977  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
978  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
979  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
980  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
981  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
982  }
983}
984
985bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
986                                          Type *Ty2) const {
987  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
988    return false;
989
990  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
991}
992
993bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
994  if (!VT1.isInteger() || !VT2.isInteger())
995    return false;
996
997  return (VT1.getSizeInBits() > VT2.getSizeInBits());
998}
999
1000bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1001  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1002  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1003}
1004
1005bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1006  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1007  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1008}
1009
1010//===----------------------------------------------------------------------===//
1011//  Other Lowering Code
1012//===----------------------------------------------------------------------===//
1013
1014MachineBasicBlock*
1015MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1016                                     MachineBasicBlock *BB) const {
1017  MachineFunction *F = BB->getParent();
1018  MachineRegisterInfo &RI = F->getRegInfo();
1019  DebugLoc dl = MI->getDebugLoc();
1020  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1021
1022  unsigned Opc;
1023  const TargetRegisterClass * RC;
1024  switch (MI->getOpcode()) {
1025  default:
1026    assert(0 && "Invalid shift opcode!");
1027  case MSP430::Shl8:
1028   Opc = MSP430::SHL8r1;
1029   RC = MSP430::GR8RegisterClass;
1030   break;
1031  case MSP430::Shl16:
1032   Opc = MSP430::SHL16r1;
1033   RC = MSP430::GR16RegisterClass;
1034   break;
1035  case MSP430::Sra8:
1036   Opc = MSP430::SAR8r1;
1037   RC = MSP430::GR8RegisterClass;
1038   break;
1039  case MSP430::Sra16:
1040   Opc = MSP430::SAR16r1;
1041   RC = MSP430::GR16RegisterClass;
1042   break;
1043  case MSP430::Srl8:
1044   Opc = MSP430::SAR8r1c;
1045   RC = MSP430::GR8RegisterClass;
1046   break;
1047  case MSP430::Srl16:
1048   Opc = MSP430::SAR16r1c;
1049   RC = MSP430::GR16RegisterClass;
1050   break;
1051  }
1052
1053  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1054  MachineFunction::iterator I = BB;
1055  ++I;
1056
1057  // Create loop block
1058  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1059  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1060
1061  F->insert(I, LoopBB);
1062  F->insert(I, RemBB);
1063
1064  // Update machine-CFG edges by transferring all successors of the current
1065  // block to the block containing instructions after shift.
1066  RemBB->splice(RemBB->begin(), BB,
1067                llvm::next(MachineBasicBlock::iterator(MI)),
1068                BB->end());
1069  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1070
1071  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1072  BB->addSuccessor(LoopBB);
1073  BB->addSuccessor(RemBB);
1074  LoopBB->addSuccessor(RemBB);
1075  LoopBB->addSuccessor(LoopBB);
1076
1077  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1078  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1079  unsigned ShiftReg = RI.createVirtualRegister(RC);
1080  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1081  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1082  unsigned SrcReg = MI->getOperand(1).getReg();
1083  unsigned DstReg = MI->getOperand(0).getReg();
1084
1085  // BB:
1086  // cmp 0, N
1087  // je RemBB
1088  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1089    .addReg(ShiftAmtSrcReg).addImm(0);
1090  BuildMI(BB, dl, TII.get(MSP430::JCC))
1091    .addMBB(RemBB)
1092    .addImm(MSP430CC::COND_E);
1093
1094  // LoopBB:
1095  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1096  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1097  // ShiftReg2 = shift ShiftReg
1098  // ShiftAmt2 = ShiftAmt - 1;
1099  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1100    .addReg(SrcReg).addMBB(BB)
1101    .addReg(ShiftReg2).addMBB(LoopBB);
1102  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1103    .addReg(ShiftAmtSrcReg).addMBB(BB)
1104    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1105  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1106    .addReg(ShiftReg);
1107  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1108    .addReg(ShiftAmtReg).addImm(1);
1109  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1110    .addMBB(LoopBB)
1111    .addImm(MSP430CC::COND_NE);
1112
1113  // RemBB:
1114  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1115  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1116    .addReg(SrcReg).addMBB(BB)
1117    .addReg(ShiftReg2).addMBB(LoopBB);
1118
1119  MI->eraseFromParent();   // The pseudo instruction is gone now.
1120  return RemBB;
1121}
1122
1123MachineBasicBlock*
1124MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1125                                                  MachineBasicBlock *BB) const {
1126  unsigned Opc = MI->getOpcode();
1127
1128  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1129      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1130      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1131    return EmitShiftInstr(MI, BB);
1132
1133  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1134  DebugLoc dl = MI->getDebugLoc();
1135
1136  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1137         "Unexpected instr type to insert");
1138
1139  // To "insert" a SELECT instruction, we actually have to insert the diamond
1140  // control-flow pattern.  The incoming instruction knows the destination vreg
1141  // to set, the condition code register to branch on, the true/false values to
1142  // select between, and a branch opcode to use.
1143  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1144  MachineFunction::iterator I = BB;
1145  ++I;
1146
1147  //  thisMBB:
1148  //  ...
1149  //   TrueVal = ...
1150  //   cmpTY ccX, r1, r2
1151  //   jCC copy1MBB
1152  //   fallthrough --> copy0MBB
1153  MachineBasicBlock *thisMBB = BB;
1154  MachineFunction *F = BB->getParent();
1155  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1156  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1157  F->insert(I, copy0MBB);
1158  F->insert(I, copy1MBB);
1159  // Update machine-CFG edges by transferring all successors of the current
1160  // block to the new block which will contain the Phi node for the select.
1161  copy1MBB->splice(copy1MBB->begin(), BB,
1162                   llvm::next(MachineBasicBlock::iterator(MI)),
1163                   BB->end());
1164  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1165  // Next, add the true and fallthrough blocks as its successors.
1166  BB->addSuccessor(copy0MBB);
1167  BB->addSuccessor(copy1MBB);
1168
1169  BuildMI(BB, dl, TII.get(MSP430::JCC))
1170    .addMBB(copy1MBB)
1171    .addImm(MI->getOperand(3).getImm());
1172
1173  //  copy0MBB:
1174  //   %FalseValue = ...
1175  //   # fallthrough to copy1MBB
1176  BB = copy0MBB;
1177
1178  // Update machine-CFG edges
1179  BB->addSuccessor(copy1MBB);
1180
1181  //  copy1MBB:
1182  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1183  //  ...
1184  BB = copy1MBB;
1185  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1186          MI->getOperand(0).getReg())
1187    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1188    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1189
1190  MI->eraseFromParent();   // The pseudo instruction is gone now.
1191  return BB;
1192}
1193