MSP430ISelLowering.cpp revision d858e90f039f5fcdc2fa93035e911a5a9505cc50 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  // Even if we have only 1 bit shift here, we can perform
81  // shifts of the whole bitwidth 1 bit per step.
82  setShiftAmountType(MVT::i8);
83
84  setStackPointerRegisterToSaveRestore(MSP430::SPW);
85  setBooleanContents(ZeroOrOneBooleanContent);
86  setSchedulingPreference(SchedulingForLatency);
87
88  // We have post-incremented loads / stores.
89  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
91
92  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
93  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
94  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
95  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
96  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
97
98  // We don't have any truncstores
99  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
100
101  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
102  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
103  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
104  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
105  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
106  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
107  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
108  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
109  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
110  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
111  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
112  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
113  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
114  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
115  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
116  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
117  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
118  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
119  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
120  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
121  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
122  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
123  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
124  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
125  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
127
128  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
129  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
130  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
131  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
132  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
133  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
134
135  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
140  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
141
142  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
143
144  // FIXME: Implement efficiently multiplication by a constant
145  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
146  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
147  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
148  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
149  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
150  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
151  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
152  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
153  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
154  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
155
156  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
157  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
158  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
159  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
160  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
161  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
162  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
163  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
164  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
165  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
166  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
167  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
168
169  // Libcalls names.
170  if (HWMultMode == HWMultIntr) {
171    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
172    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173  } else if (HWMultMode == HWMultNoIntr) {
174    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
175    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
176  }
177}
178
179SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
180                                             SelectionDAG &DAG) const {
181  switch (Op.getOpcode()) {
182  case ISD::SHL: // FALLTHROUGH
183  case ISD::SRL:
184  case ISD::SRA:              return LowerShifts(Op, DAG);
185  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
186  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
187  case ISD::SETCC:            return LowerSETCC(Op, DAG);
188  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
189  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
190  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
191  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
192  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
193  default:
194    llvm_unreachable("unimplemented operand");
195    return SDValue();
196  }
197}
198
199/// getFunctionAlignment - Return the Log2 alignment of this function.
200unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
201  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
202}
203
204//===----------------------------------------------------------------------===//
205//                       MSP430 Inline Assembly Support
206//===----------------------------------------------------------------------===//
207
208/// getConstraintType - Given a constraint letter, return the type of
209/// constraint it is for this target.
210TargetLowering::ConstraintType
211MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
212  if (Constraint.size() == 1) {
213    switch (Constraint[0]) {
214    case 'r':
215      return C_RegisterClass;
216    default:
217      break;
218    }
219  }
220  return TargetLowering::getConstraintType(Constraint);
221}
222
223std::pair<unsigned, const TargetRegisterClass*>
224MSP430TargetLowering::
225getRegForInlineAsmConstraint(const std::string &Constraint,
226                             EVT VT) const {
227  if (Constraint.size() == 1) {
228    // GCC Constraint Letters
229    switch (Constraint[0]) {
230    default: break;
231    case 'r':   // GENERAL_REGS
232      if (VT == MVT::i8)
233        return std::make_pair(0U, MSP430::GR8RegisterClass);
234
235      return std::make_pair(0U, MSP430::GR16RegisterClass);
236    }
237  }
238
239  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
240}
241
242//===----------------------------------------------------------------------===//
243//                      Calling Convention Implementation
244//===----------------------------------------------------------------------===//
245
246#include "MSP430GenCallingConv.inc"
247
248SDValue
249MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
250                                           CallingConv::ID CallConv,
251                                           bool isVarArg,
252                                           const SmallVectorImpl<ISD::InputArg>
253                                             &Ins,
254                                           DebugLoc dl,
255                                           SelectionDAG &DAG,
256                                           SmallVectorImpl<SDValue> &InVals)
257                                             const {
258
259  switch (CallConv) {
260  default:
261    llvm_unreachable("Unsupported calling convention");
262  case CallingConv::C:
263  case CallingConv::Fast:
264    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
265  case CallingConv::MSP430_INTR:
266   if (Ins.empty())
267     return Chain;
268   else {
269    report_fatal_error("ISRs cannot have arguments");
270    return SDValue();
271   }
272  }
273}
274
275SDValue
276MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
277                                CallingConv::ID CallConv, bool isVarArg,
278                                bool &isTailCall,
279                                const SmallVectorImpl<ISD::OutputArg> &Outs,
280                                const SmallVectorImpl<ISD::InputArg> &Ins,
281                                DebugLoc dl, SelectionDAG &DAG,
282                                SmallVectorImpl<SDValue> &InVals) const {
283  // MSP430 target does not yet support tail call optimization.
284  isTailCall = false;
285
286  switch (CallConv) {
287  default:
288    llvm_unreachable("Unsupported calling convention");
289  case CallingConv::Fast:
290  case CallingConv::C:
291    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
292                          Outs, Ins, dl, DAG, InVals);
293  case CallingConv::MSP430_INTR:
294    report_fatal_error("ISRs cannot be called directly");
295    return SDValue();
296  }
297}
298
299/// LowerCCCArguments - transform physical registers into virtual registers and
300/// generate load operations for arguments places on the stack.
301// FIXME: struct return stuff
302// FIXME: varargs
303SDValue
304MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
305                                        CallingConv::ID CallConv,
306                                        bool isVarArg,
307                                        const SmallVectorImpl<ISD::InputArg>
308                                          &Ins,
309                                        DebugLoc dl,
310                                        SelectionDAG &DAG,
311                                        SmallVectorImpl<SDValue> &InVals)
312                                          const {
313  MachineFunction &MF = DAG.getMachineFunction();
314  MachineFrameInfo *MFI = MF.getFrameInfo();
315  MachineRegisterInfo &RegInfo = MF.getRegInfo();
316
317  // Assign locations to all of the incoming arguments.
318  SmallVector<CCValAssign, 16> ArgLocs;
319  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
320                 ArgLocs, *DAG.getContext());
321  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
322
323  assert(!isVarArg && "Varargs not supported yet");
324
325  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
326    CCValAssign &VA = ArgLocs[i];
327    if (VA.isRegLoc()) {
328      // Arguments passed in registers
329      EVT RegVT = VA.getLocVT();
330      switch (RegVT.getSimpleVT().SimpleTy) {
331      default:
332        {
333#ifndef NDEBUG
334          errs() << "LowerFormalArguments Unhandled argument type: "
335               << RegVT.getSimpleVT().SimpleTy << "\n";
336#endif
337          llvm_unreachable(0);
338        }
339      case MVT::i16:
340        unsigned VReg =
341          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
342        RegInfo.addLiveIn(VA.getLocReg(), VReg);
343        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
344
345        // If this is an 8-bit value, it is really passed promoted to 16
346        // bits. Insert an assert[sz]ext to capture this, then truncate to the
347        // right size.
348        if (VA.getLocInfo() == CCValAssign::SExt)
349          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
350                                 DAG.getValueType(VA.getValVT()));
351        else if (VA.getLocInfo() == CCValAssign::ZExt)
352          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
353                                 DAG.getValueType(VA.getValVT()));
354
355        if (VA.getLocInfo() != CCValAssign::Full)
356          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
357
358        InVals.push_back(ArgValue);
359      }
360    } else {
361      // Sanity check
362      assert(VA.isMemLoc());
363      // Load the argument to a virtual register
364      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
365      if (ObjSize > 2) {
366        errs() << "LowerFormalArguments Unhandled argument type: "
367             << VA.getLocVT().getSimpleVT().SimpleTy
368             << "\n";
369      }
370      // Create the frame index object for this incoming parameter...
371      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
372
373      // Create the SelectionDAG nodes corresponding to a load
374      //from this parameter
375      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
376      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
377                                   PseudoSourceValue::getFixedStack(FI), 0,
378                                   false, false, 0));
379    }
380  }
381
382  return Chain;
383}
384
385SDValue
386MSP430TargetLowering::LowerReturn(SDValue Chain,
387                                  CallingConv::ID CallConv, bool isVarArg,
388                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
389                                  DebugLoc dl, SelectionDAG &DAG) const {
390
391  // CCValAssign - represent the assignment of the return value to a location
392  SmallVector<CCValAssign, 16> RVLocs;
393
394  // ISRs cannot return any value.
395  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
396    report_fatal_error("ISRs cannot return any value");
397    return SDValue();
398  }
399
400  // CCState - Info about the registers and stack slot.
401  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
402                 RVLocs, *DAG.getContext());
403
404  // Analize return values.
405  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
406
407  // If this is the first return lowered for this function, add the regs to the
408  // liveout set for the function.
409  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
410    for (unsigned i = 0; i != RVLocs.size(); ++i)
411      if (RVLocs[i].isRegLoc())
412        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
413  }
414
415  SDValue Flag;
416
417  // Copy the result values into the output registers.
418  for (unsigned i = 0; i != RVLocs.size(); ++i) {
419    CCValAssign &VA = RVLocs[i];
420    assert(VA.isRegLoc() && "Can only return in registers!");
421
422    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
423                             Outs[i].Val, Flag);
424
425    // Guarantee that all emitted copies are stuck together,
426    // avoiding something bad.
427    Flag = Chain.getValue(1);
428  }
429
430  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
431                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
432
433  if (Flag.getNode())
434    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
435
436  // Return Void
437  return DAG.getNode(Opc, dl, MVT::Other, Chain);
438}
439
440/// LowerCCCCallTo - functions arguments are copied from virtual regs to
441/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
442/// TODO: sret.
443SDValue
444MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
445                                     CallingConv::ID CallConv, bool isVarArg,
446                                     bool isTailCall,
447                                     const SmallVectorImpl<ISD::OutputArg>
448                                       &Outs,
449                                     const SmallVectorImpl<ISD::InputArg> &Ins,
450                                     DebugLoc dl, SelectionDAG &DAG,
451                                     SmallVectorImpl<SDValue> &InVals) const {
452  // Analyze operands of the call, assigning locations to each operand.
453  SmallVector<CCValAssign, 16> ArgLocs;
454  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
455                 ArgLocs, *DAG.getContext());
456
457  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
458
459  // Get a count of how many bytes are to be pushed on the stack.
460  unsigned NumBytes = CCInfo.getNextStackOffset();
461
462  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
463                                                      getPointerTy(), true));
464
465  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
466  SmallVector<SDValue, 12> MemOpChains;
467  SDValue StackPtr;
468
469  // Walk the register/memloc assignments, inserting copies/loads.
470  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
471    CCValAssign &VA = ArgLocs[i];
472
473    SDValue Arg = Outs[i].Val;
474
475    // Promote the value if needed.
476    switch (VA.getLocInfo()) {
477      default: llvm_unreachable("Unknown loc info!");
478      case CCValAssign::Full: break;
479      case CCValAssign::SExt:
480        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
481        break;
482      case CCValAssign::ZExt:
483        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
484        break;
485      case CCValAssign::AExt:
486        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
487        break;
488    }
489
490    // Arguments that can be passed on register must be kept at RegsToPass
491    // vector
492    if (VA.isRegLoc()) {
493      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
494    } else {
495      assert(VA.isMemLoc());
496
497      if (StackPtr.getNode() == 0)
498        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
499
500      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
501                                   StackPtr,
502                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
503
504
505      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
506                                         PseudoSourceValue::getStack(),
507                                         VA.getLocMemOffset(), false, false, 0));
508    }
509  }
510
511  // Transform all store nodes into one single node because all store nodes are
512  // independent of each other.
513  if (!MemOpChains.empty())
514    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
515                        &MemOpChains[0], MemOpChains.size());
516
517  // Build a sequence of copy-to-reg nodes chained together with token chain and
518  // flag operands which copy the outgoing args into registers.  The InFlag in
519  // necessary since all emited instructions must be stuck together.
520  SDValue InFlag;
521  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
522    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
523                             RegsToPass[i].second, InFlag);
524    InFlag = Chain.getValue(1);
525  }
526
527  // If the callee is a GlobalAddress node (quite common, every direct call is)
528  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
529  // Likewise ExternalSymbol -> TargetExternalSymbol.
530  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
531    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
532  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
533    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
534
535  // Returns a chain & a flag for retval copy to use.
536  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
537  SmallVector<SDValue, 8> Ops;
538  Ops.push_back(Chain);
539  Ops.push_back(Callee);
540
541  // Add argument registers to the end of the list so that they are
542  // known live into the call.
543  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
544    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
545                                  RegsToPass[i].second.getValueType()));
546
547  if (InFlag.getNode())
548    Ops.push_back(InFlag);
549
550  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
551  InFlag = Chain.getValue(1);
552
553  // Create the CALLSEQ_END node.
554  Chain = DAG.getCALLSEQ_END(Chain,
555                             DAG.getConstant(NumBytes, getPointerTy(), true),
556                             DAG.getConstant(0, getPointerTy(), true),
557                             InFlag);
558  InFlag = Chain.getValue(1);
559
560  // Handle result values, copying them out of physregs into vregs that we
561  // return.
562  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
563                         DAG, InVals);
564}
565
566/// LowerCallResult - Lower the result values of a call into the
567/// appropriate copies out of appropriate physical registers.
568///
569SDValue
570MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
571                                      CallingConv::ID CallConv, bool isVarArg,
572                                      const SmallVectorImpl<ISD::InputArg> &Ins,
573                                      DebugLoc dl, SelectionDAG &DAG,
574                                      SmallVectorImpl<SDValue> &InVals) const {
575
576  // Assign locations to each value returned by this call.
577  SmallVector<CCValAssign, 16> RVLocs;
578  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
579                 RVLocs, *DAG.getContext());
580
581  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
582
583  // Copy all of the result registers out of their specified physreg.
584  for (unsigned i = 0; i != RVLocs.size(); ++i) {
585    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
586                               RVLocs[i].getValVT(), InFlag).getValue(1);
587    InFlag = Chain.getValue(2);
588    InVals.push_back(Chain.getValue(0));
589  }
590
591  return Chain;
592}
593
594SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
595                                          SelectionDAG &DAG) const {
596  unsigned Opc = Op.getOpcode();
597  SDNode* N = Op.getNode();
598  EVT VT = Op.getValueType();
599  DebugLoc dl = N->getDebugLoc();
600
601  // Expand non-constant shifts to loops:
602  if (!isa<ConstantSDNode>(N->getOperand(1)))
603    switch (Opc) {
604    default:
605      assert(0 && "Invalid shift opcode!");
606    case ISD::SHL:
607      return DAG.getNode(MSP430ISD::SHL, dl,
608                         VT, N->getOperand(0), N->getOperand(1));
609    case ISD::SRA:
610      return DAG.getNode(MSP430ISD::SRA, dl,
611                         VT, N->getOperand(0), N->getOperand(1));
612    case ISD::SRL:
613      return DAG.getNode(MSP430ISD::SRL, dl,
614                         VT, N->getOperand(0), N->getOperand(1));
615    }
616
617  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
618
619  // Expand the stuff into sequence of shifts.
620  // FIXME: for some shift amounts this might be done better!
621  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
622  SDValue Victim = N->getOperand(0);
623
624  if (Opc == ISD::SRL && ShiftAmount) {
625    // Emit a special goodness here:
626    // srl A, 1 => clrc; rrc A
627    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
628    ShiftAmount -= 1;
629  }
630
631  while (ShiftAmount--)
632    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
633                         dl, VT, Victim);
634
635  return Victim;
636}
637
638SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
639                                                 SelectionDAG &DAG) const {
640  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
641  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
642
643  // Create the TargetGlobalAddress node, folding in the constant offset.
644  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
645  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
646                     getPointerTy(), Result);
647}
648
649SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
650                                                  SelectionDAG &DAG) const {
651  DebugLoc dl = Op.getDebugLoc();
652  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
653  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
654
655  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
656}
657
658static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
659                       ISD::CondCode CC,
660                       DebugLoc dl, SelectionDAG &DAG) {
661  // FIXME: Handle bittests someday
662  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
663
664  // FIXME: Handle jump negative someday
665  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
666  switch (CC) {
667  default: llvm_unreachable("Invalid integer condition!");
668  case ISD::SETEQ:
669    TCC = MSP430CC::COND_E;     // aka COND_Z
670    // Minor optimization: if LHS is a constant, swap operands, then the
671    // constant can be folded into comparison.
672    if (LHS.getOpcode() == ISD::Constant)
673      std::swap(LHS, RHS);
674    break;
675  case ISD::SETNE:
676    TCC = MSP430CC::COND_NE;    // aka COND_NZ
677    // Minor optimization: if LHS is a constant, swap operands, then the
678    // constant can be folded into comparison.
679    if (LHS.getOpcode() == ISD::Constant)
680      std::swap(LHS, RHS);
681    break;
682  case ISD::SETULE:
683    std::swap(LHS, RHS);        // FALLTHROUGH
684  case ISD::SETUGE:
685    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
686    // fold constant into instruction.
687    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
688      LHS = RHS;
689      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
690      TCC = MSP430CC::COND_LO;
691      break;
692    }
693    TCC = MSP430CC::COND_HS;    // aka COND_C
694    break;
695  case ISD::SETUGT:
696    std::swap(LHS, RHS);        // FALLTHROUGH
697  case ISD::SETULT:
698    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
699    // fold constant into instruction.
700    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
701      LHS = RHS;
702      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
703      TCC = MSP430CC::COND_HS;
704      break;
705    }
706    TCC = MSP430CC::COND_LO;    // aka COND_NC
707    break;
708  case ISD::SETLE:
709    std::swap(LHS, RHS);        // FALLTHROUGH
710  case ISD::SETGE:
711    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
712    // fold constant into instruction.
713    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
714      LHS = RHS;
715      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
716      TCC = MSP430CC::COND_L;
717      break;
718    }
719    TCC = MSP430CC::COND_GE;
720    break;
721  case ISD::SETGT:
722    std::swap(LHS, RHS);        // FALLTHROUGH
723  case ISD::SETLT:
724    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
725    // fold constant into instruction.
726    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
727      LHS = RHS;
728      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
729      TCC = MSP430CC::COND_GE;
730      break;
731    }
732    TCC = MSP430CC::COND_L;
733    break;
734  }
735
736  TargetCC = DAG.getConstant(TCC, MVT::i8);
737  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
738}
739
740
741SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
742  SDValue Chain = Op.getOperand(0);
743  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
744  SDValue LHS   = Op.getOperand(2);
745  SDValue RHS   = Op.getOperand(3);
746  SDValue Dest  = Op.getOperand(4);
747  DebugLoc dl   = Op.getDebugLoc();
748
749  SDValue TargetCC;
750  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
751
752  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
753                     Chain, Dest, TargetCC, Flag);
754}
755
756
757SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
758  SDValue LHS   = Op.getOperand(0);
759  SDValue RHS   = Op.getOperand(1);
760  DebugLoc dl   = Op.getDebugLoc();
761
762  // If we are doing an AND and testing against zero, then the CMP
763  // will not be generated.  The AND (or BIT) will generate the condition codes,
764  // but they are different from CMP.
765  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
766  // lowering & isel wouldn't diverge.
767  bool andCC = false;
768  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
769    if (RHSC->isNullValue() && LHS.hasOneUse() &&
770        (LHS.getOpcode() == ISD::AND ||
771         (LHS.getOpcode() == ISD::TRUNCATE &&
772          LHS.getOperand(0).getOpcode() == ISD::AND))) {
773      andCC = true;
774    }
775  }
776  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
777  SDValue TargetCC;
778  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
779
780  // Get the condition codes directly from the status register, if its easy.
781  // Otherwise a branch will be generated.  Note that the AND and BIT
782  // instructions generate different flags than CMP, the carry bit can be used
783  // for NE/EQ.
784  bool Invert = false;
785  bool Shift = false;
786  bool Convert = true;
787  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
788   default:
789    Convert = false;
790    break;
791   case MSP430CC::COND_HS:
792     // Res = SRW & 1, no processing is required
793     break;
794   case MSP430CC::COND_LO:
795     // Res = ~(SRW & 1)
796     Invert = true;
797     break;
798   case MSP430CC::COND_NE:
799     if (andCC) {
800       // C = ~Z, thus Res = SRW & 1, no processing is required
801     } else {
802       // Res = ~((SRW >> 1) & 1)
803       Shift = true;
804       Invert = true;
805     }
806     break;
807   case MSP430CC::COND_E:
808     Shift = true;
809     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
810     // Res = (SRW >> 1) & 1 is 1 word shorter.
811     break;
812  }
813  EVT VT = Op.getValueType();
814  SDValue One  = DAG.getConstant(1, VT);
815  if (Convert) {
816    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
817                                    MVT::i16, Flag);
818    if (Shift)
819      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
820      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
821    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
822    if (Invert)
823      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
824    return SR;
825  } else {
826    SDValue Zero = DAG.getConstant(0, VT);
827    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
828    SmallVector<SDValue, 4> Ops;
829    Ops.push_back(One);
830    Ops.push_back(Zero);
831    Ops.push_back(TargetCC);
832    Ops.push_back(Flag);
833    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
834  }
835}
836
837SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
838                                             SelectionDAG &DAG) const {
839  SDValue LHS    = Op.getOperand(0);
840  SDValue RHS    = Op.getOperand(1);
841  SDValue TrueV  = Op.getOperand(2);
842  SDValue FalseV = Op.getOperand(3);
843  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
844  DebugLoc dl    = Op.getDebugLoc();
845
846  SDValue TargetCC;
847  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
848
849  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
850  SmallVector<SDValue, 4> Ops;
851  Ops.push_back(TrueV);
852  Ops.push_back(FalseV);
853  Ops.push_back(TargetCC);
854  Ops.push_back(Flag);
855
856  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
857}
858
859SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
860                                               SelectionDAG &DAG) const {
861  SDValue Val = Op.getOperand(0);
862  EVT VT      = Op.getValueType();
863  DebugLoc dl = Op.getDebugLoc();
864
865  assert(VT == MVT::i16 && "Only support i16 for now!");
866
867  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
868                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
869                     DAG.getValueType(Val.getValueType()));
870}
871
872SDValue
873MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
874  MachineFunction &MF = DAG.getMachineFunction();
875  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
876  int ReturnAddrIndex = FuncInfo->getRAIndex();
877
878  if (ReturnAddrIndex == 0) {
879    // Set up a frame object for the return address.
880    uint64_t SlotSize = TD->getPointerSize();
881    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
882                                                           true, false);
883    FuncInfo->setRAIndex(ReturnAddrIndex);
884  }
885
886  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
887}
888
889SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
890                                              SelectionDAG &DAG) const {
891  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
892  DebugLoc dl = Op.getDebugLoc();
893
894  if (Depth > 0) {
895    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
896    SDValue Offset =
897      DAG.getConstant(TD->getPointerSize(), MVT::i16);
898    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
899                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
900                                   FrameAddr, Offset),
901                       NULL, 0, false, false, 0);
902  }
903
904  // Just load the return address.
905  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
906  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
907                     RetAddrFI, NULL, 0, false, false, 0);
908}
909
910SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
911                                             SelectionDAG &DAG) const {
912  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
913  MFI->setFrameAddressIsTaken(true);
914  EVT VT = Op.getValueType();
915  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
916  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
917  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
918                                         MSP430::FPW, VT);
919  while (Depth--)
920    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
921                            false, false, 0);
922  return FrameAddr;
923}
924
925/// getPostIndexedAddressParts - returns true by value, base pointer and
926/// offset pointer and addressing mode by reference if this node can be
927/// combined with a load / store to form a post-indexed load / store.
928bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
929                                                      SDValue &Base,
930                                                      SDValue &Offset,
931                                                      ISD::MemIndexedMode &AM,
932                                                      SelectionDAG &DAG) const {
933
934  LoadSDNode *LD = cast<LoadSDNode>(N);
935  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
936    return false;
937
938  EVT VT = LD->getMemoryVT();
939  if (VT != MVT::i8 && VT != MVT::i16)
940    return false;
941
942  if (Op->getOpcode() != ISD::ADD)
943    return false;
944
945  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
946    uint64_t RHSC = RHS->getZExtValue();
947    if ((VT == MVT::i16 && RHSC != 2) ||
948        (VT == MVT::i8 && RHSC != 1))
949      return false;
950
951    Base = Op->getOperand(0);
952    Offset = DAG.getConstant(RHSC, VT);
953    AM = ISD::POST_INC;
954    return true;
955  }
956
957  return false;
958}
959
960
961const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
962  switch (Opcode) {
963  default: return NULL;
964  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
965  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
966  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
967  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
968  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
969  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
970  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
971  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
972  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
973  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
974  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
975  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
976  }
977}
978
979bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
980                                          const Type *Ty2) const {
981  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
982    return false;
983
984  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
985}
986
987bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
988  if (!VT1.isInteger() || !VT2.isInteger())
989    return false;
990
991  return (VT1.getSizeInBits() > VT2.getSizeInBits());
992}
993
994bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
995  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
996  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
997}
998
999bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1000  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1001  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1002}
1003
1004//===----------------------------------------------------------------------===//
1005//  Other Lowering Code
1006//===----------------------------------------------------------------------===//
1007
1008MachineBasicBlock*
1009MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1010                                     MachineBasicBlock *BB,
1011                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1012  MachineFunction *F = BB->getParent();
1013  MachineRegisterInfo &RI = F->getRegInfo();
1014  DebugLoc dl = MI->getDebugLoc();
1015  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1016
1017  unsigned Opc;
1018  const TargetRegisterClass * RC;
1019  switch (MI->getOpcode()) {
1020  default:
1021    assert(0 && "Invalid shift opcode!");
1022  case MSP430::Shl8:
1023   Opc = MSP430::SHL8r1;
1024   RC = MSP430::GR8RegisterClass;
1025   break;
1026  case MSP430::Shl16:
1027   Opc = MSP430::SHL16r1;
1028   RC = MSP430::GR16RegisterClass;
1029   break;
1030  case MSP430::Sra8:
1031   Opc = MSP430::SAR8r1;
1032   RC = MSP430::GR8RegisterClass;
1033   break;
1034  case MSP430::Sra16:
1035   Opc = MSP430::SAR16r1;
1036   RC = MSP430::GR16RegisterClass;
1037   break;
1038  case MSP430::Srl8:
1039   Opc = MSP430::SAR8r1c;
1040   RC = MSP430::GR8RegisterClass;
1041   break;
1042  case MSP430::Srl16:
1043   Opc = MSP430::SAR16r1c;
1044   RC = MSP430::GR16RegisterClass;
1045   break;
1046  }
1047
1048  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1049  MachineFunction::iterator I = BB;
1050  ++I;
1051
1052  // Create loop block
1053  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1054  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1055
1056  F->insert(I, LoopBB);
1057  F->insert(I, RemBB);
1058
1059  // Update machine-CFG edges by transferring all successors of the current
1060  // block to the block containing instructions after shift.
1061  RemBB->transferSuccessors(BB);
1062
1063  // Inform sdisel of the edge changes.
1064  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1065         SE = BB->succ_end(); SI != SE; ++SI)
1066    EM->insert(std::make_pair(*SI, RemBB));
1067
1068  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1069  BB->addSuccessor(LoopBB);
1070  BB->addSuccessor(RemBB);
1071  LoopBB->addSuccessor(RemBB);
1072  LoopBB->addSuccessor(LoopBB);
1073
1074  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1075  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1076  unsigned ShiftReg = RI.createVirtualRegister(RC);
1077  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1078  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1079  unsigned SrcReg = MI->getOperand(1).getReg();
1080  unsigned DstReg = MI->getOperand(0).getReg();
1081
1082  // BB:
1083  // cmp 0, N
1084  // je RemBB
1085  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1086    .addReg(ShiftAmtSrcReg).addImm(0);
1087  BuildMI(BB, dl, TII.get(MSP430::JCC))
1088    .addMBB(RemBB)
1089    .addImm(MSP430CC::COND_E);
1090
1091  // LoopBB:
1092  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1093  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1094  // ShiftReg2 = shift ShiftReg
1095  // ShiftAmt2 = ShiftAmt - 1;
1096  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1097    .addReg(SrcReg).addMBB(BB)
1098    .addReg(ShiftReg2).addMBB(LoopBB);
1099  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1100    .addReg(ShiftAmtSrcReg).addMBB(BB)
1101    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1102  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1103    .addReg(ShiftReg);
1104  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1105    .addReg(ShiftAmtReg).addImm(1);
1106  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1107    .addMBB(LoopBB)
1108    .addImm(MSP430CC::COND_NE);
1109
1110  // RemBB:
1111  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1112  BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
1113    .addReg(SrcReg).addMBB(BB)
1114    .addReg(ShiftReg2).addMBB(LoopBB);
1115
1116  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1117  return RemBB;
1118}
1119
1120MachineBasicBlock*
1121MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1122                                                  MachineBasicBlock *BB,
1123                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
1124  unsigned Opc = MI->getOpcode();
1125
1126  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1127      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1128      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1129    return EmitShiftInstr(MI, BB, EM);
1130
1131  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1132  DebugLoc dl = MI->getDebugLoc();
1133
1134  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1135         "Unexpected instr type to insert");
1136
1137  // To "insert" a SELECT instruction, we actually have to insert the diamond
1138  // control-flow pattern.  The incoming instruction knows the destination vreg
1139  // to set, the condition code register to branch on, the true/false values to
1140  // select between, and a branch opcode to use.
1141  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1142  MachineFunction::iterator I = BB;
1143  ++I;
1144
1145  //  thisMBB:
1146  //  ...
1147  //   TrueVal = ...
1148  //   cmpTY ccX, r1, r2
1149  //   jCC copy1MBB
1150  //   fallthrough --> copy0MBB
1151  MachineBasicBlock *thisMBB = BB;
1152  MachineFunction *F = BB->getParent();
1153  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1154  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1155  BuildMI(BB, dl, TII.get(MSP430::JCC))
1156    .addMBB(copy1MBB)
1157    .addImm(MI->getOperand(3).getImm());
1158  F->insert(I, copy0MBB);
1159  F->insert(I, copy1MBB);
1160  // Inform sdisel of the edge changes.
1161  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
1162         SE = BB->succ_end(); SI != SE; ++SI)
1163    EM->insert(std::make_pair(*SI, copy1MBB));
1164  // Update machine-CFG edges by transferring all successors of the current
1165  // block to the new block which will contain the Phi node for the select.
1166  copy1MBB->transferSuccessors(BB);
1167  // Next, add the true and fallthrough blocks as its successors.
1168  BB->addSuccessor(copy0MBB);
1169  BB->addSuccessor(copy1MBB);
1170
1171  //  copy0MBB:
1172  //   %FalseValue = ...
1173  //   # fallthrough to copy1MBB
1174  BB = copy0MBB;
1175
1176  // Update machine-CFG edges
1177  BB->addSuccessor(copy1MBB);
1178
1179  //  copy1MBB:
1180  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1181  //  ...
1182  BB = copy1MBB;
1183  BuildMI(BB, dl, TII.get(MSP430::PHI),
1184          MI->getOperand(0).getReg())
1185    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1186    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1187
1188  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1189  return BB;
1190}
1191