MSP430ISelLowering.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MSP430ISelLowering.h"
15#include "MSP430.h"
16#include "MSP430MachineFunctionInfo.h"
17#include "MSP430Subtarget.h"
18#include "MSP430TargetMachine.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/SelectionDAGISel.h"
25#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/IR/CallingConv.h"
28#include "llvm/IR/DerivedTypes.h"
29#include "llvm/IR/Function.h"
30#include "llvm/IR/GlobalAlias.h"
31#include "llvm/IR/GlobalVariable.h"
32#include "llvm/IR/Intrinsics.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37using namespace llvm;
38
39#define DEBUG_TYPE "msp430-lower"
40
41typedef enum {
42  NoHWMult,
43  HWMultIntr,
44  HWMultNoIntr
45} HWMultUseMode;
46
47static cl::opt<HWMultUseMode>
48HWMultMode("msp430-hwmult-mode", cl::Hidden,
49           cl::desc("Hardware multiplier use mode"),
50           cl::init(HWMultNoIntr),
51           cl::values(
52             clEnumValN(NoHWMult, "no",
53                "Do not use hardware multiplier"),
54             clEnumValN(HWMultIntr, "interrupts",
55                "Assume hardware multiplier can be used inside interrupts"),
56             clEnumValN(HWMultNoIntr, "use",
57                "Assume hardware multiplier cannot be used inside interrupts"),
58             clEnumValEnd));
59
60MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
61  TargetLowering(tm, new TargetLoweringObjectFileELF()),
62  Subtarget(*tm.getSubtargetImpl()) {
63
64  TD = getDataLayout();
65
66  // Set up the register classes.
67  addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
68  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
69
70  // Compute derived properties from the register classes
71  computeRegisterProperties();
72
73  // Provide all sorts of operation actions
74
75  // Division is expensive
76  setIntDivIsCheap(false);
77
78  setStackPointerRegisterToSaveRestore(MSP430::SPW);
79  setBooleanContents(ZeroOrOneBooleanContent);
80  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
81
82  // We have post-incremented loads / stores.
83  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
85
86  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
88  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
89  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
90  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
91
92  // We don't have any truncstores
93  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
96  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
97  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
98  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
99  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
100  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
101  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
102  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
103  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
104  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
105  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
106  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
107  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
108  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
110  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
111  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
112  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
113  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
114  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
115  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
116  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
117  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
118  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
119  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
123  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
124  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i8,    Expand);
125  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i16,   Expand);
126  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
128  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i8,    Expand);
129  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i16,   Expand);
130  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
131  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
132
133  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
134  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
135  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
139
140  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
141
142  // FIXME: Implement efficiently multiplication by a constant
143  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
144  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
145  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
146  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
147  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
148  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
149  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
150  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
151  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
152  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
153
154  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
155  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
156  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
157  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
158  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
159  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
160  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
161  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
162  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
163  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
164  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
165  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
166
167  // varargs support
168  setOperationAction(ISD::VASTART,          MVT::Other, Custom);
169  setOperationAction(ISD::VAARG,            MVT::Other, Expand);
170  setOperationAction(ISD::VAEND,            MVT::Other, Expand);
171  setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
172  setOperationAction(ISD::JumpTable,        MVT::i16,   Custom);
173
174  // Libcalls names.
175  if (HWMultMode == HWMultIntr) {
176    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
177    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
178  } else if (HWMultMode == HWMultNoIntr) {
179    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
180    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
181  }
182
183  setMinFunctionAlignment(1);
184  setPrefFunctionAlignment(2);
185}
186
187SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
188                                             SelectionDAG &DAG) const {
189  switch (Op.getOpcode()) {
190  case ISD::SHL: // FALLTHROUGH
191  case ISD::SRL:
192  case ISD::SRA:              return LowerShifts(Op, DAG);
193  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
194  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
195  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
196  case ISD::SETCC:            return LowerSETCC(Op, DAG);
197  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
198  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
199  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
200  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
201  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
202  case ISD::VASTART:          return LowerVASTART(Op, DAG);
203  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
204  default:
205    llvm_unreachable("unimplemented operand");
206  }
207}
208
209//===----------------------------------------------------------------------===//
210//                       MSP430 Inline Assembly Support
211//===----------------------------------------------------------------------===//
212
213/// getConstraintType - Given a constraint letter, return the type of
214/// constraint it is for this target.
215TargetLowering::ConstraintType
216MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
217  if (Constraint.size() == 1) {
218    switch (Constraint[0]) {
219    case 'r':
220      return C_RegisterClass;
221    default:
222      break;
223    }
224  }
225  return TargetLowering::getConstraintType(Constraint);
226}
227
228std::pair<unsigned, const TargetRegisterClass*>
229MSP430TargetLowering::
230getRegForInlineAsmConstraint(const std::string &Constraint,
231                             MVT VT) const {
232  if (Constraint.size() == 1) {
233    // GCC Constraint Letters
234    switch (Constraint[0]) {
235    default: break;
236    case 'r':   // GENERAL_REGS
237      if (VT == MVT::i8)
238        return std::make_pair(0U, &MSP430::GR8RegClass);
239
240      return std::make_pair(0U, &MSP430::GR16RegClass);
241    }
242  }
243
244  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
245}
246
247//===----------------------------------------------------------------------===//
248//                      Calling Convention Implementation
249//===----------------------------------------------------------------------===//
250
251#include "MSP430GenCallingConv.inc"
252
253/// For each argument in a function store the number of pieces it is composed
254/// of.
255template<typename ArgT>
256static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
257                              SmallVectorImpl<unsigned> &Out) {
258  unsigned CurrentArgIndex = ~0U;
259  for (unsigned i = 0, e = Args.size(); i != e; i++) {
260    if (CurrentArgIndex == Args[i].OrigArgIndex) {
261      Out.back()++;
262    } else {
263      Out.push_back(1);
264      CurrentArgIndex++;
265    }
266  }
267}
268
269static void AnalyzeVarArgs(CCState &State,
270                           const SmallVectorImpl<ISD::OutputArg> &Outs) {
271  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
272}
273
274static void AnalyzeVarArgs(CCState &State,
275                           const SmallVectorImpl<ISD::InputArg> &Ins) {
276  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
277}
278
279/// Analyze incoming and outgoing function arguments. We need custom C++ code
280/// to handle special constraints in the ABI like reversing the order of the
281/// pieces of splitted arguments. In addition, all pieces of a certain argument
282/// have to be passed either using registers or the stack but never mixing both.
283template<typename ArgT>
284static void AnalyzeArguments(CCState &State,
285                             SmallVectorImpl<CCValAssign> &ArgLocs,
286                             const SmallVectorImpl<ArgT> &Args) {
287  static const MCPhysReg RegList[] = {
288    MSP430::R15W, MSP430::R14W, MSP430::R13W, MSP430::R12W
289  };
290  static const unsigned NbRegs = array_lengthof(RegList);
291
292  if (State.isVarArg()) {
293    AnalyzeVarArgs(State, Args);
294    return;
295  }
296
297  SmallVector<unsigned, 4> ArgsParts;
298  ParseFunctionArgs(Args, ArgsParts);
299
300  unsigned RegsLeft = NbRegs;
301  bool UseStack = false;
302  unsigned ValNo = 0;
303
304  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
305    MVT ArgVT = Args[ValNo].VT;
306    ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
307    MVT LocVT = ArgVT;
308    CCValAssign::LocInfo LocInfo = CCValAssign::Full;
309
310    // Promote i8 to i16
311    if (LocVT == MVT::i8) {
312      LocVT = MVT::i16;
313      if (ArgFlags.isSExt())
314          LocInfo = CCValAssign::SExt;
315      else if (ArgFlags.isZExt())
316          LocInfo = CCValAssign::ZExt;
317      else
318          LocInfo = CCValAssign::AExt;
319    }
320
321    // Handle byval arguments
322    if (ArgFlags.isByVal()) {
323      State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
324      continue;
325    }
326
327    unsigned Parts = ArgsParts[i];
328
329    if (!UseStack && Parts <= RegsLeft) {
330      unsigned FirstVal = ValNo;
331      for (unsigned j = 0; j < Parts; j++) {
332        unsigned Reg = State.AllocateReg(RegList, NbRegs);
333        State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
334        RegsLeft--;
335      }
336
337      // Reverse the order of the pieces to agree with the "big endian" format
338      // required in the calling convention ABI.
339      SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
340      std::reverse(B, B + Parts);
341    } else {
342      UseStack = true;
343      for (unsigned j = 0; j < Parts; j++)
344        CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
345    }
346  }
347}
348
349static void AnalyzeRetResult(CCState &State,
350                             const SmallVectorImpl<ISD::InputArg> &Ins) {
351  State.AnalyzeCallResult(Ins, RetCC_MSP430);
352}
353
354static void AnalyzeRetResult(CCState &State,
355                             const SmallVectorImpl<ISD::OutputArg> &Outs) {
356  State.AnalyzeReturn(Outs, RetCC_MSP430);
357}
358
359template<typename ArgT>
360static void AnalyzeReturnValues(CCState &State,
361                                SmallVectorImpl<CCValAssign> &RVLocs,
362                                const SmallVectorImpl<ArgT> &Args) {
363  AnalyzeRetResult(State, Args);
364
365  // Reverse splitted return values to get the "big endian" format required
366  // to agree with the calling convention ABI.
367  std::reverse(RVLocs.begin(), RVLocs.end());
368}
369
370SDValue
371MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
372                                           CallingConv::ID CallConv,
373                                           bool isVarArg,
374                                           const SmallVectorImpl<ISD::InputArg>
375                                             &Ins,
376                                           SDLoc dl,
377                                           SelectionDAG &DAG,
378                                           SmallVectorImpl<SDValue> &InVals)
379                                             const {
380
381  switch (CallConv) {
382  default:
383    llvm_unreachable("Unsupported calling convention");
384  case CallingConv::C:
385  case CallingConv::Fast:
386    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
387  case CallingConv::MSP430_INTR:
388    if (Ins.empty())
389      return Chain;
390    report_fatal_error("ISRs cannot have arguments");
391  }
392}
393
394SDValue
395MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
396                                SmallVectorImpl<SDValue> &InVals) const {
397  SelectionDAG &DAG                     = CLI.DAG;
398  SDLoc &dl                             = CLI.DL;
399  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
400  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
401  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
402  SDValue Chain                         = CLI.Chain;
403  SDValue Callee                        = CLI.Callee;
404  bool &isTailCall                      = CLI.IsTailCall;
405  CallingConv::ID CallConv              = CLI.CallConv;
406  bool isVarArg                         = CLI.IsVarArg;
407
408  // MSP430 target does not yet support tail call optimization.
409  isTailCall = false;
410
411  switch (CallConv) {
412  default:
413    llvm_unreachable("Unsupported calling convention");
414  case CallingConv::Fast:
415  case CallingConv::C:
416    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
417                          Outs, OutVals, Ins, dl, DAG, InVals);
418  case CallingConv::MSP430_INTR:
419    report_fatal_error("ISRs cannot be called directly");
420  }
421}
422
423/// LowerCCCArguments - transform physical registers into virtual registers and
424/// generate load operations for arguments places on the stack.
425// FIXME: struct return stuff
426SDValue
427MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
428                                        CallingConv::ID CallConv,
429                                        bool isVarArg,
430                                        const SmallVectorImpl<ISD::InputArg>
431                                          &Ins,
432                                        SDLoc dl,
433                                        SelectionDAG &DAG,
434                                        SmallVectorImpl<SDValue> &InVals)
435                                          const {
436  MachineFunction &MF = DAG.getMachineFunction();
437  MachineFrameInfo *MFI = MF.getFrameInfo();
438  MachineRegisterInfo &RegInfo = MF.getRegInfo();
439  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
440
441  // Assign locations to all of the incoming arguments.
442  SmallVector<CCValAssign, 16> ArgLocs;
443  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
444                 getTargetMachine(), ArgLocs, *DAG.getContext());
445  AnalyzeArguments(CCInfo, ArgLocs, Ins);
446
447  // Create frame index for the start of the first vararg value
448  if (isVarArg) {
449    unsigned Offset = CCInfo.getNextStackOffset();
450    FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
451  }
452
453  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
454    CCValAssign &VA = ArgLocs[i];
455    if (VA.isRegLoc()) {
456      // Arguments passed in registers
457      EVT RegVT = VA.getLocVT();
458      switch (RegVT.getSimpleVT().SimpleTy) {
459      default:
460        {
461#ifndef NDEBUG
462          errs() << "LowerFormalArguments Unhandled argument type: "
463               << RegVT.getSimpleVT().SimpleTy << "\n";
464#endif
465          llvm_unreachable(nullptr);
466        }
467      case MVT::i16:
468        unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
469        RegInfo.addLiveIn(VA.getLocReg(), VReg);
470        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
471
472        // If this is an 8-bit value, it is really passed promoted to 16
473        // bits. Insert an assert[sz]ext to capture this, then truncate to the
474        // right size.
475        if (VA.getLocInfo() == CCValAssign::SExt)
476          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
477                                 DAG.getValueType(VA.getValVT()));
478        else if (VA.getLocInfo() == CCValAssign::ZExt)
479          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
480                                 DAG.getValueType(VA.getValVT()));
481
482        if (VA.getLocInfo() != CCValAssign::Full)
483          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
484
485        InVals.push_back(ArgValue);
486      }
487    } else {
488      // Sanity check
489      assert(VA.isMemLoc());
490
491      SDValue InVal;
492      ISD::ArgFlagsTy Flags = Ins[i].Flags;
493
494      if (Flags.isByVal()) {
495        int FI = MFI->CreateFixedObject(Flags.getByValSize(),
496                                        VA.getLocMemOffset(), true);
497        InVal = DAG.getFrameIndex(FI, getPointerTy());
498      } else {
499        // Load the argument to a virtual register
500        unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
501        if (ObjSize > 2) {
502            errs() << "LowerFormalArguments Unhandled argument type: "
503                << EVT(VA.getLocVT()).getEVTString()
504                << "\n";
505        }
506        // Create the frame index object for this incoming parameter...
507        int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
508
509        // Create the SelectionDAG nodes corresponding to a load
510        //from this parameter
511        SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
512        InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
513                            MachinePointerInfo::getFixedStack(FI),
514                            false, false, false, 0);
515      }
516
517      InVals.push_back(InVal);
518    }
519  }
520
521  return Chain;
522}
523
524SDValue
525MSP430TargetLowering::LowerReturn(SDValue Chain,
526                                  CallingConv::ID CallConv, bool isVarArg,
527                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
528                                  const SmallVectorImpl<SDValue> &OutVals,
529                                  SDLoc dl, SelectionDAG &DAG) const {
530
531  // CCValAssign - represent the assignment of the return value to a location
532  SmallVector<CCValAssign, 16> RVLocs;
533
534  // ISRs cannot return any value.
535  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
536    report_fatal_error("ISRs cannot return any value");
537
538  // CCState - Info about the registers and stack slot.
539  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
540                 getTargetMachine(), RVLocs, *DAG.getContext());
541
542  // Analize return values.
543  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
544
545  SDValue Flag;
546  SmallVector<SDValue, 4> RetOps(1, Chain);
547
548  // Copy the result values into the output registers.
549  for (unsigned i = 0; i != RVLocs.size(); ++i) {
550    CCValAssign &VA = RVLocs[i];
551    assert(VA.isRegLoc() && "Can only return in registers!");
552
553    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
554                             OutVals[i], Flag);
555
556    // Guarantee that all emitted copies are stuck together,
557    // avoiding something bad.
558    Flag = Chain.getValue(1);
559    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
560  }
561
562  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
563                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
564
565  RetOps[0] = Chain;  // Update chain.
566
567  // Add the flag if we have it.
568  if (Flag.getNode())
569    RetOps.push_back(Flag);
570
571  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
572}
573
574/// LowerCCCCallTo - functions arguments are copied from virtual regs to
575/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
576// TODO: sret.
577SDValue
578MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
579                                     CallingConv::ID CallConv, bool isVarArg,
580                                     bool isTailCall,
581                                     const SmallVectorImpl<ISD::OutputArg>
582                                       &Outs,
583                                     const SmallVectorImpl<SDValue> &OutVals,
584                                     const SmallVectorImpl<ISD::InputArg> &Ins,
585                                     SDLoc dl, SelectionDAG &DAG,
586                                     SmallVectorImpl<SDValue> &InVals) const {
587  // Analyze operands of the call, assigning locations to each operand.
588  SmallVector<CCValAssign, 16> ArgLocs;
589  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
590                 getTargetMachine(), ArgLocs, *DAG.getContext());
591  AnalyzeArguments(CCInfo, ArgLocs, Outs);
592
593  // Get a count of how many bytes are to be pushed on the stack.
594  unsigned NumBytes = CCInfo.getNextStackOffset();
595
596  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
597                                                      getPointerTy(), true),
598                               dl);
599
600  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
601  SmallVector<SDValue, 12> MemOpChains;
602  SDValue StackPtr;
603
604  // Walk the register/memloc assignments, inserting copies/loads.
605  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
606    CCValAssign &VA = ArgLocs[i];
607
608    SDValue Arg = OutVals[i];
609
610    // Promote the value if needed.
611    switch (VA.getLocInfo()) {
612      default: llvm_unreachable("Unknown loc info!");
613      case CCValAssign::Full: break;
614      case CCValAssign::SExt:
615        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
616        break;
617      case CCValAssign::ZExt:
618        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
619        break;
620      case CCValAssign::AExt:
621        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
622        break;
623    }
624
625    // Arguments that can be passed on register must be kept at RegsToPass
626    // vector
627    if (VA.isRegLoc()) {
628      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
629    } else {
630      assert(VA.isMemLoc());
631
632      if (!StackPtr.getNode())
633        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
634
635      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
636                                   StackPtr,
637                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
638
639      SDValue MemOp;
640      ISD::ArgFlagsTy Flags = Outs[i].Flags;
641
642      if (Flags.isByVal()) {
643        SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
644        MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
645                              Flags.getByValAlign(),
646                              /*isVolatile*/false,
647                              /*AlwaysInline=*/true,
648                              MachinePointerInfo(),
649                              MachinePointerInfo());
650      } else {
651        MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
652                             false, false, 0);
653      }
654
655      MemOpChains.push_back(MemOp);
656    }
657  }
658
659  // Transform all store nodes into one single node because all store nodes are
660  // independent of each other.
661  if (!MemOpChains.empty())
662    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
663
664  // Build a sequence of copy-to-reg nodes chained together with token chain and
665  // flag operands which copy the outgoing args into registers.  The InFlag in
666  // necessary since all emitted instructions must be stuck together.
667  SDValue InFlag;
668  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
669    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
670                             RegsToPass[i].second, InFlag);
671    InFlag = Chain.getValue(1);
672  }
673
674  // If the callee is a GlobalAddress node (quite common, every direct call is)
675  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
676  // Likewise ExternalSymbol -> TargetExternalSymbol.
677  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
678    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
679  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
680    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
681
682  // Returns a chain & a flag for retval copy to use.
683  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
684  SmallVector<SDValue, 8> Ops;
685  Ops.push_back(Chain);
686  Ops.push_back(Callee);
687
688  // Add argument registers to the end of the list so that they are
689  // known live into the call.
690  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
691    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
692                                  RegsToPass[i].second.getValueType()));
693
694  if (InFlag.getNode())
695    Ops.push_back(InFlag);
696
697  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
698  InFlag = Chain.getValue(1);
699
700  // Create the CALLSEQ_END node.
701  Chain = DAG.getCALLSEQ_END(Chain,
702                             DAG.getConstant(NumBytes, getPointerTy(), true),
703                             DAG.getConstant(0, getPointerTy(), true),
704                             InFlag, dl);
705  InFlag = Chain.getValue(1);
706
707  // Handle result values, copying them out of physregs into vregs that we
708  // return.
709  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
710                         DAG, InVals);
711}
712
713/// LowerCallResult - Lower the result values of a call into the
714/// appropriate copies out of appropriate physical registers.
715///
716SDValue
717MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
718                                      CallingConv::ID CallConv, bool isVarArg,
719                                      const SmallVectorImpl<ISD::InputArg> &Ins,
720                                      SDLoc dl, SelectionDAG &DAG,
721                                      SmallVectorImpl<SDValue> &InVals) const {
722
723  // Assign locations to each value returned by this call.
724  SmallVector<CCValAssign, 16> RVLocs;
725  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
726                 getTargetMachine(), RVLocs, *DAG.getContext());
727
728  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
729
730  // Copy all of the result registers out of their specified physreg.
731  for (unsigned i = 0; i != RVLocs.size(); ++i) {
732    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
733                               RVLocs[i].getValVT(), InFlag).getValue(1);
734    InFlag = Chain.getValue(2);
735    InVals.push_back(Chain.getValue(0));
736  }
737
738  return Chain;
739}
740
741SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
742                                          SelectionDAG &DAG) const {
743  unsigned Opc = Op.getOpcode();
744  SDNode* N = Op.getNode();
745  EVT VT = Op.getValueType();
746  SDLoc dl(N);
747
748  // Expand non-constant shifts to loops:
749  if (!isa<ConstantSDNode>(N->getOperand(1)))
750    switch (Opc) {
751    default: llvm_unreachable("Invalid shift opcode!");
752    case ISD::SHL:
753      return DAG.getNode(MSP430ISD::SHL, dl,
754                         VT, N->getOperand(0), N->getOperand(1));
755    case ISD::SRA:
756      return DAG.getNode(MSP430ISD::SRA, dl,
757                         VT, N->getOperand(0), N->getOperand(1));
758    case ISD::SRL:
759      return DAG.getNode(MSP430ISD::SRL, dl,
760                         VT, N->getOperand(0), N->getOperand(1));
761    }
762
763  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
764
765  // Expand the stuff into sequence of shifts.
766  // FIXME: for some shift amounts this might be done better!
767  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
768  SDValue Victim = N->getOperand(0);
769
770  if (Opc == ISD::SRL && ShiftAmount) {
771    // Emit a special goodness here:
772    // srl A, 1 => clrc; rrc A
773    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
774    ShiftAmount -= 1;
775  }
776
777  while (ShiftAmount--)
778    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
779                         dl, VT, Victim);
780
781  return Victim;
782}
783
784SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
785                                                 SelectionDAG &DAG) const {
786  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
787  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
788
789  // Create the TargetGlobalAddress node, folding in the constant offset.
790  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
791                                              getPointerTy(), Offset);
792  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op),
793                     getPointerTy(), Result);
794}
795
796SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
797                                                  SelectionDAG &DAG) const {
798  SDLoc dl(Op);
799  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
800  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
801
802  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
803}
804
805SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
806                                                SelectionDAG &DAG) const {
807  SDLoc dl(Op);
808  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
809  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
810
811  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
812}
813
814static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
815                       ISD::CondCode CC,
816                       SDLoc dl, SelectionDAG &DAG) {
817  // FIXME: Handle bittests someday
818  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
819
820  // FIXME: Handle jump negative someday
821  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
822  switch (CC) {
823  default: llvm_unreachable("Invalid integer condition!");
824  case ISD::SETEQ:
825    TCC = MSP430CC::COND_E;     // aka COND_Z
826    // Minor optimization: if LHS is a constant, swap operands, then the
827    // constant can be folded into comparison.
828    if (LHS.getOpcode() == ISD::Constant)
829      std::swap(LHS, RHS);
830    break;
831  case ISD::SETNE:
832    TCC = MSP430CC::COND_NE;    // aka COND_NZ
833    // Minor optimization: if LHS is a constant, swap operands, then the
834    // constant can be folded into comparison.
835    if (LHS.getOpcode() == ISD::Constant)
836      std::swap(LHS, RHS);
837    break;
838  case ISD::SETULE:
839    std::swap(LHS, RHS);        // FALLTHROUGH
840  case ISD::SETUGE:
841    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
842    // fold constant into instruction.
843    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
844      LHS = RHS;
845      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
846      TCC = MSP430CC::COND_LO;
847      break;
848    }
849    TCC = MSP430CC::COND_HS;    // aka COND_C
850    break;
851  case ISD::SETUGT:
852    std::swap(LHS, RHS);        // FALLTHROUGH
853  case ISD::SETULT:
854    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
855    // fold constant into instruction.
856    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
857      LHS = RHS;
858      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
859      TCC = MSP430CC::COND_HS;
860      break;
861    }
862    TCC = MSP430CC::COND_LO;    // aka COND_NC
863    break;
864  case ISD::SETLE:
865    std::swap(LHS, RHS);        // FALLTHROUGH
866  case ISD::SETGE:
867    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
868    // fold constant into instruction.
869    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
870      LHS = RHS;
871      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
872      TCC = MSP430CC::COND_L;
873      break;
874    }
875    TCC = MSP430CC::COND_GE;
876    break;
877  case ISD::SETGT:
878    std::swap(LHS, RHS);        // FALLTHROUGH
879  case ISD::SETLT:
880    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
881    // fold constant into instruction.
882    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
883      LHS = RHS;
884      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
885      TCC = MSP430CC::COND_GE;
886      break;
887    }
888    TCC = MSP430CC::COND_L;
889    break;
890  }
891
892  TargetCC = DAG.getConstant(TCC, MVT::i8);
893  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
894}
895
896
897SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
898  SDValue Chain = Op.getOperand(0);
899  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
900  SDValue LHS   = Op.getOperand(2);
901  SDValue RHS   = Op.getOperand(3);
902  SDValue Dest  = Op.getOperand(4);
903  SDLoc dl  (Op);
904
905  SDValue TargetCC;
906  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
907
908  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
909                     Chain, Dest, TargetCC, Flag);
910}
911
912SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
913  SDValue LHS   = Op.getOperand(0);
914  SDValue RHS   = Op.getOperand(1);
915  SDLoc dl  (Op);
916
917  // If we are doing an AND and testing against zero, then the CMP
918  // will not be generated.  The AND (or BIT) will generate the condition codes,
919  // but they are different from CMP.
920  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
921  // lowering & isel wouldn't diverge.
922  bool andCC = false;
923  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
924    if (RHSC->isNullValue() && LHS.hasOneUse() &&
925        (LHS.getOpcode() == ISD::AND ||
926         (LHS.getOpcode() == ISD::TRUNCATE &&
927          LHS.getOperand(0).getOpcode() == ISD::AND))) {
928      andCC = true;
929    }
930  }
931  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
932  SDValue TargetCC;
933  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
934
935  // Get the condition codes directly from the status register, if its easy.
936  // Otherwise a branch will be generated.  Note that the AND and BIT
937  // instructions generate different flags than CMP, the carry bit can be used
938  // for NE/EQ.
939  bool Invert = false;
940  bool Shift = false;
941  bool Convert = true;
942  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
943   default:
944    Convert = false;
945    break;
946   case MSP430CC::COND_HS:
947     // Res = SRW & 1, no processing is required
948     break;
949   case MSP430CC::COND_LO:
950     // Res = ~(SRW & 1)
951     Invert = true;
952     break;
953   case MSP430CC::COND_NE:
954     if (andCC) {
955       // C = ~Z, thus Res = SRW & 1, no processing is required
956     } else {
957       // Res = ~((SRW >> 1) & 1)
958       Shift = true;
959       Invert = true;
960     }
961     break;
962   case MSP430CC::COND_E:
963     Shift = true;
964     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
965     // Res = (SRW >> 1) & 1 is 1 word shorter.
966     break;
967  }
968  EVT VT = Op.getValueType();
969  SDValue One  = DAG.getConstant(1, VT);
970  if (Convert) {
971    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
972                                    MVT::i16, Flag);
973    if (Shift)
974      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
975      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
976    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
977    if (Invert)
978      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
979    return SR;
980  } else {
981    SDValue Zero = DAG.getConstant(0, VT);
982    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
983    SmallVector<SDValue, 4> Ops;
984    Ops.push_back(One);
985    Ops.push_back(Zero);
986    Ops.push_back(TargetCC);
987    Ops.push_back(Flag);
988    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
989  }
990}
991
992SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
993                                             SelectionDAG &DAG) const {
994  SDValue LHS    = Op.getOperand(0);
995  SDValue RHS    = Op.getOperand(1);
996  SDValue TrueV  = Op.getOperand(2);
997  SDValue FalseV = Op.getOperand(3);
998  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
999  SDLoc dl   (Op);
1000
1001  SDValue TargetCC;
1002  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1003
1004  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1005  SmallVector<SDValue, 4> Ops;
1006  Ops.push_back(TrueV);
1007  Ops.push_back(FalseV);
1008  Ops.push_back(TargetCC);
1009  Ops.push_back(Flag);
1010
1011  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1012}
1013
1014SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1015                                               SelectionDAG &DAG) const {
1016  SDValue Val = Op.getOperand(0);
1017  EVT VT      = Op.getValueType();
1018  SDLoc dl(Op);
1019
1020  assert(VT == MVT::i16 && "Only support i16 for now!");
1021
1022  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1023                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1024                     DAG.getValueType(Val.getValueType()));
1025}
1026
1027SDValue
1028MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1029  MachineFunction &MF = DAG.getMachineFunction();
1030  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1031  int ReturnAddrIndex = FuncInfo->getRAIndex();
1032
1033  if (ReturnAddrIndex == 0) {
1034    // Set up a frame object for the return address.
1035    uint64_t SlotSize = TD->getPointerSize();
1036    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
1037                                                           true);
1038    FuncInfo->setRAIndex(ReturnAddrIndex);
1039  }
1040
1041  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1042}
1043
1044SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1045                                              SelectionDAG &DAG) const {
1046  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1047  MFI->setReturnAddressIsTaken(true);
1048
1049  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1050    return SDValue();
1051
1052  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1053  SDLoc dl(Op);
1054
1055  if (Depth > 0) {
1056    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1057    SDValue Offset =
1058      DAG.getConstant(TD->getPointerSize(), MVT::i16);
1059    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1060                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
1061                                   FrameAddr, Offset),
1062                       MachinePointerInfo(), false, false, false, 0);
1063  }
1064
1065  // Just load the return address.
1066  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1067  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1068                     RetAddrFI, MachinePointerInfo(), false, false, false, 0);
1069}
1070
1071SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1072                                             SelectionDAG &DAG) const {
1073  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1074  MFI->setFrameAddressIsTaken(true);
1075
1076  EVT VT = Op.getValueType();
1077  SDLoc dl(Op);  // FIXME probably not meaningful
1078  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1079  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1080                                         MSP430::FPW, VT);
1081  while (Depth--)
1082    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1083                            MachinePointerInfo(),
1084                            false, false, false, 0);
1085  return FrameAddr;
1086}
1087
1088SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1089                                           SelectionDAG &DAG) const {
1090  MachineFunction &MF = DAG.getMachineFunction();
1091  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1092
1093  // Frame index of first vararg argument
1094  SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1095                                         getPointerTy());
1096  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1097
1098  // Create a store of the frame index to the location operand
1099  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex,
1100                      Op.getOperand(1), MachinePointerInfo(SV),
1101                      false, false, 0);
1102}
1103
1104SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1105                                             SelectionDAG &DAG) const {
1106    JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1107    SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
1108    return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT),
1109                       getPointerTy(), Result);
1110}
1111
1112/// getPostIndexedAddressParts - returns true by value, base pointer and
1113/// offset pointer and addressing mode by reference if this node can be
1114/// combined with a load / store to form a post-indexed load / store.
1115bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1116                                                      SDValue &Base,
1117                                                      SDValue &Offset,
1118                                                      ISD::MemIndexedMode &AM,
1119                                                      SelectionDAG &DAG) const {
1120
1121  LoadSDNode *LD = cast<LoadSDNode>(N);
1122  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1123    return false;
1124
1125  EVT VT = LD->getMemoryVT();
1126  if (VT != MVT::i8 && VT != MVT::i16)
1127    return false;
1128
1129  if (Op->getOpcode() != ISD::ADD)
1130    return false;
1131
1132  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1133    uint64_t RHSC = RHS->getZExtValue();
1134    if ((VT == MVT::i16 && RHSC != 2) ||
1135        (VT == MVT::i8 && RHSC != 1))
1136      return false;
1137
1138    Base = Op->getOperand(0);
1139    Offset = DAG.getConstant(RHSC, VT);
1140    AM = ISD::POST_INC;
1141    return true;
1142  }
1143
1144  return false;
1145}
1146
1147
1148const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1149  switch (Opcode) {
1150  default: return nullptr;
1151  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1152  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1153  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1154  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1155  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1156  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1157  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1158  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1159  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1160  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1161  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
1162  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
1163  }
1164}
1165
1166bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1167                                          Type *Ty2) const {
1168  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1169    return false;
1170
1171  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1172}
1173
1174bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1175  if (!VT1.isInteger() || !VT2.isInteger())
1176    return false;
1177
1178  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1179}
1180
1181bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1182  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1183  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1184}
1185
1186bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1187  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1188  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1189}
1190
1191bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1192  return isZExtFree(Val.getValueType(), VT2);
1193}
1194
1195//===----------------------------------------------------------------------===//
1196//  Other Lowering Code
1197//===----------------------------------------------------------------------===//
1198
1199MachineBasicBlock*
1200MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1201                                     MachineBasicBlock *BB) const {
1202  MachineFunction *F = BB->getParent();
1203  MachineRegisterInfo &RI = F->getRegInfo();
1204  DebugLoc dl = MI->getDebugLoc();
1205  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1206
1207  unsigned Opc;
1208  const TargetRegisterClass * RC;
1209  switch (MI->getOpcode()) {
1210  default: llvm_unreachable("Invalid shift opcode!");
1211  case MSP430::Shl8:
1212   Opc = MSP430::SHL8r1;
1213   RC = &MSP430::GR8RegClass;
1214   break;
1215  case MSP430::Shl16:
1216   Opc = MSP430::SHL16r1;
1217   RC = &MSP430::GR16RegClass;
1218   break;
1219  case MSP430::Sra8:
1220   Opc = MSP430::SAR8r1;
1221   RC = &MSP430::GR8RegClass;
1222   break;
1223  case MSP430::Sra16:
1224   Opc = MSP430::SAR16r1;
1225   RC = &MSP430::GR16RegClass;
1226   break;
1227  case MSP430::Srl8:
1228   Opc = MSP430::SAR8r1c;
1229   RC = &MSP430::GR8RegClass;
1230   break;
1231  case MSP430::Srl16:
1232   Opc = MSP430::SAR16r1c;
1233   RC = &MSP430::GR16RegClass;
1234   break;
1235  }
1236
1237  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1238  MachineFunction::iterator I = BB;
1239  ++I;
1240
1241  // Create loop block
1242  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1243  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1244
1245  F->insert(I, LoopBB);
1246  F->insert(I, RemBB);
1247
1248  // Update machine-CFG edges by transferring all successors of the current
1249  // block to the block containing instructions after shift.
1250  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1251                BB->end());
1252  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1253
1254  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1255  BB->addSuccessor(LoopBB);
1256  BB->addSuccessor(RemBB);
1257  LoopBB->addSuccessor(RemBB);
1258  LoopBB->addSuccessor(LoopBB);
1259
1260  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1261  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1262  unsigned ShiftReg = RI.createVirtualRegister(RC);
1263  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1264  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1265  unsigned SrcReg = MI->getOperand(1).getReg();
1266  unsigned DstReg = MI->getOperand(0).getReg();
1267
1268  // BB:
1269  // cmp 0, N
1270  // je RemBB
1271  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1272    .addReg(ShiftAmtSrcReg).addImm(0);
1273  BuildMI(BB, dl, TII.get(MSP430::JCC))
1274    .addMBB(RemBB)
1275    .addImm(MSP430CC::COND_E);
1276
1277  // LoopBB:
1278  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1279  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1280  // ShiftReg2 = shift ShiftReg
1281  // ShiftAmt2 = ShiftAmt - 1;
1282  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1283    .addReg(SrcReg).addMBB(BB)
1284    .addReg(ShiftReg2).addMBB(LoopBB);
1285  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1286    .addReg(ShiftAmtSrcReg).addMBB(BB)
1287    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1288  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1289    .addReg(ShiftReg);
1290  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1291    .addReg(ShiftAmtReg).addImm(1);
1292  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1293    .addMBB(LoopBB)
1294    .addImm(MSP430CC::COND_NE);
1295
1296  // RemBB:
1297  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1298  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1299    .addReg(SrcReg).addMBB(BB)
1300    .addReg(ShiftReg2).addMBB(LoopBB);
1301
1302  MI->eraseFromParent();   // The pseudo instruction is gone now.
1303  return RemBB;
1304}
1305
1306MachineBasicBlock*
1307MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1308                                                  MachineBasicBlock *BB) const {
1309  unsigned Opc = MI->getOpcode();
1310
1311  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1312      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1313      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1314    return EmitShiftInstr(MI, BB);
1315
1316  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1317  DebugLoc dl = MI->getDebugLoc();
1318
1319  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1320         "Unexpected instr type to insert");
1321
1322  // To "insert" a SELECT instruction, we actually have to insert the diamond
1323  // control-flow pattern.  The incoming instruction knows the destination vreg
1324  // to set, the condition code register to branch on, the true/false values to
1325  // select between, and a branch opcode to use.
1326  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1327  MachineFunction::iterator I = BB;
1328  ++I;
1329
1330  //  thisMBB:
1331  //  ...
1332  //   TrueVal = ...
1333  //   cmpTY ccX, r1, r2
1334  //   jCC copy1MBB
1335  //   fallthrough --> copy0MBB
1336  MachineBasicBlock *thisMBB = BB;
1337  MachineFunction *F = BB->getParent();
1338  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1339  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1340  F->insert(I, copy0MBB);
1341  F->insert(I, copy1MBB);
1342  // Update machine-CFG edges by transferring all successors of the current
1343  // block to the new block which will contain the Phi node for the select.
1344  copy1MBB->splice(copy1MBB->begin(), BB,
1345                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1346  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1347  // Next, add the true and fallthrough blocks as its successors.
1348  BB->addSuccessor(copy0MBB);
1349  BB->addSuccessor(copy1MBB);
1350
1351  BuildMI(BB, dl, TII.get(MSP430::JCC))
1352    .addMBB(copy1MBB)
1353    .addImm(MI->getOperand(3).getImm());
1354
1355  //  copy0MBB:
1356  //   %FalseValue = ...
1357  //   # fallthrough to copy1MBB
1358  BB = copy0MBB;
1359
1360  // Update machine-CFG edges
1361  BB->addSuccessor(copy1MBB);
1362
1363  //  copy1MBB:
1364  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1365  //  ...
1366  BB = copy1MBB;
1367  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1368          MI->getOperand(0).getReg())
1369    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1370    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1371
1372  MI->eraseFromParent();   // The pseudo instruction is gone now.
1373  return BB;
1374}
1375