MSP430ISelLowering.h revision 8d1ffbd1adad453fe330be4951400bfd25fab666 
1//==-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ------*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that MSP430 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_MSP430_ISELLOWERING_H
16#define LLVM_TARGET_MSP430_ISELLOWERING_H
17
18#include "MSP430.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23  namespace MSP430ISD {
24    enum {
25      FIRST_NUMBER = ISD::BUILTIN_OP_END,
26
27      /// Return with a flag operand. Operand 0 is the chain operand.
28      RET_FLAG,
29
30      /// Same as RET_FLAG, but used for returning from ISRs.
31      RETI_FLAG,
32
33      /// Y = R{R,L}A X, rotate right (left) arithmetically
34      RRA, RLA,
35
36      /// Y = RRC X, rotate right via carry
37      RRC,
38
39      /// CALL - These operations represent an abstract call
40      /// instruction, which includes a bunch of information.
41      CALL,
42
43      /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
44      /// and TargetGlobalAddress.
45      Wrapper,
46
47      /// CMP - Compare instruction.
48      CMP,
49
50      /// SetCC. Operand 0 is condition code, and operand 1 is the flag
51      /// operand produced by a CMP instruction.
52      SETCC,
53
54      /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
55      /// is the block to branch if condition is true, operand 2 is the
56      /// condition code, and operand 3 is the flag operand produced by a CMP
57      /// instruction.
58      BR_CC,
59
60      /// SELECT_CC. Operand 0 and operand 1 are selection variable, operand 3
61      /// is condition code and operand 4 is flag operand.
62      SELECT_CC
63    };
64  }
65
66  class MSP430Subtarget;
67  class MSP430TargetMachine;
68
69  class MSP430TargetLowering : public TargetLowering {
70  public:
71    explicit MSP430TargetLowering(MSP430TargetMachine &TM);
72
73    /// LowerOperation - Provide custom lowering hooks for some operations.
74    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
75
76    /// getTargetNodeName - This method returns the name of a target specific
77    /// DAG node.
78    virtual const char *getTargetNodeName(unsigned Opcode) const;
79
80    /// getFunctionAlignment - Return the Log2 alignment of this function.
81    virtual unsigned getFunctionAlignment(const Function *F) const;
82
83    SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
84    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
85    SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG);
86    SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
87    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
88    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
89    SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG);
90    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
91    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
92    SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
93
94    TargetLowering::ConstraintType
95    getConstraintType(const std::string &Constraint) const;
96    std::pair<unsigned, const TargetRegisterClass*>
97    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
98
99    MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
100                                                   MachineBasicBlock *BB,
101                    DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
102
103  private:
104    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
105                           CallingConv::ID CallConv, bool isVarArg,
106                           bool isTailCall,
107                           const SmallVectorImpl<ISD::OutputArg> &Outs,
108                           const SmallVectorImpl<ISD::InputArg> &Ins,
109                           DebugLoc dl, SelectionDAG &DAG,
110                           SmallVectorImpl<SDValue> &InVals);
111
112    SDValue LowerCCCArguments(SDValue Chain,
113                              CallingConv::ID CallConv,
114                              bool isVarArg,
115                              const SmallVectorImpl<ISD::InputArg> &Ins,
116                              DebugLoc dl,
117                              SelectionDAG &DAG,
118                              SmallVectorImpl<SDValue> &InVals);
119
120    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
121                            CallingConv::ID CallConv, bool isVarArg,
122                            const SmallVectorImpl<ISD::InputArg> &Ins,
123                            DebugLoc dl, SelectionDAG &DAG,
124                            SmallVectorImpl<SDValue> &InVals);
125
126    virtual SDValue
127      LowerFormalArguments(SDValue Chain,
128                           CallingConv::ID CallConv, bool isVarArg,
129                           const SmallVectorImpl<ISD::InputArg> &Ins,
130                           DebugLoc dl, SelectionDAG &DAG,
131                           SmallVectorImpl<SDValue> &InVals);
132    virtual SDValue
133      LowerCall(SDValue Chain, SDValue Callee,
134                CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
135                const SmallVectorImpl<ISD::OutputArg> &Outs,
136                const SmallVectorImpl<ISD::InputArg> &Ins,
137                DebugLoc dl, SelectionDAG &DAG,
138                SmallVectorImpl<SDValue> &InVals);
139
140    virtual SDValue
141      LowerReturn(SDValue Chain,
142                  CallingConv::ID CallConv, bool isVarArg,
143                  const SmallVectorImpl<ISD::OutputArg> &Outs,
144                  DebugLoc dl, SelectionDAG &DAG);
145
146    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
147                                            SDValue &Base,
148                                            SDValue &Offset,
149                                            ISD::MemIndexedMode &AM,
150                                            SelectionDAG &DAG) const;
151
152    const MSP430Subtarget &Subtarget;
153    const MSP430TargetMachine &TM;
154    const TargetData *TD;
155  };
156} // namespace llvm
157
158#endif // LLVM_TARGET_MSP430_ISELLOWERING_H
159