MSP430InstrInfo.cpp revision 22fee2dff4c43b551aefa44a96ca74fcade6bfac 
1//===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MSP430.h"
15#include "MSP430InstrInfo.h"
16#include "MSP430MachineFunctionInfo.h"
17#include "MSP430TargetMachine.h"
18#include "llvm/Function.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/PseudoSourceValue.h"
23#include "llvm/Support/ErrorHandling.h"
24
25#define GET_INSTRINFO_MC_DESC
26#include "MSP430GenInstrInfo.inc"
27
28using namespace llvm;
29
30MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
31  : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
32    RI(tm, *this), TM(tm) {}
33
34void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
35                                          MachineBasicBlock::iterator MI,
36                                    unsigned SrcReg, bool isKill, int FrameIdx,
37                                          const TargetRegisterClass *RC,
38                                          const TargetRegisterInfo *TRI) const {
39  DebugLoc DL;
40  if (MI != MBB.end()) DL = MI->getDebugLoc();
41  MachineFunction &MF = *MBB.getParent();
42  MachineFrameInfo &MFI = *MF.getFrameInfo();
43
44  MachineMemOperand *MMO =
45    MF.getMachineMemOperand(
46              MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
47                            MachineMemOperand::MOStore,
48                            MFI.getObjectSize(FrameIdx),
49                            MFI.getObjectAlignment(FrameIdx));
50
51  if (RC == &MSP430::GR16RegClass)
52    BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
53      .addFrameIndex(FrameIdx).addImm(0)
54      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
55  else if (RC == &MSP430::GR8RegClass)
56    BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
57      .addFrameIndex(FrameIdx).addImm(0)
58      .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59  else
60    llvm_unreachable("Cannot store this register to stack slot!");
61}
62
63void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
64                                           MachineBasicBlock::iterator MI,
65                                           unsigned DestReg, int FrameIdx,
66                                           const TargetRegisterClass *RC,
67                                           const TargetRegisterInfo *TRI) const{
68  DebugLoc DL;
69  if (MI != MBB.end()) DL = MI->getDebugLoc();
70  MachineFunction &MF = *MBB.getParent();
71  MachineFrameInfo &MFI = *MF.getFrameInfo();
72
73  MachineMemOperand *MMO =
74    MF.getMachineMemOperand(
75              MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)),
76                            MachineMemOperand::MOLoad,
77                            MFI.getObjectSize(FrameIdx),
78                            MFI.getObjectAlignment(FrameIdx));
79
80  if (RC == &MSP430::GR16RegClass)
81    BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
82      .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
83  else if (RC == &MSP430::GR8RegClass)
84    BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
85      .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
86  else
87    llvm_unreachable("Cannot store this register to stack slot!");
88}
89
90void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
91                                  MachineBasicBlock::iterator I, DebugLoc DL,
92                                  unsigned DestReg, unsigned SrcReg,
93                                  bool KillSrc) const {
94  unsigned Opc;
95  if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
96    Opc = MSP430::MOV16rr;
97  else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
98    Opc = MSP430::MOV8rr;
99  else
100    llvm_unreachable("Impossible reg-to-reg copy");
101
102  BuildMI(MBB, I, DL, get(Opc), DestReg)
103    .addReg(SrcReg, getKillRegState(KillSrc));
104}
105
106unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
107  MachineBasicBlock::iterator I = MBB.end();
108  unsigned Count = 0;
109
110  while (I != MBB.begin()) {
111    --I;
112    if (I->isDebugValue())
113      continue;
114    if (I->getOpcode() != MSP430::JMP &&
115        I->getOpcode() != MSP430::JCC &&
116        I->getOpcode() != MSP430::Br &&
117        I->getOpcode() != MSP430::Bm)
118      break;
119    // Remove the branch.
120    I->eraseFromParent();
121    I = MBB.end();
122    ++Count;
123  }
124
125  return Count;
126}
127
128bool MSP430InstrInfo::
129ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
130  assert(Cond.size() == 1 && "Invalid Xbranch condition!");
131
132  MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
133
134  switch (CC) {
135  default:
136    assert(0 && "Invalid branch condition!");
137    break;
138  case MSP430CC::COND_E:
139    CC = MSP430CC::COND_NE;
140    break;
141  case MSP430CC::COND_NE:
142    CC = MSP430CC::COND_E;
143    break;
144  case MSP430CC::COND_L:
145    CC = MSP430CC::COND_GE;
146    break;
147  case MSP430CC::COND_GE:
148    CC = MSP430CC::COND_L;
149    break;
150  case MSP430CC::COND_HS:
151    CC = MSP430CC::COND_LO;
152    break;
153  case MSP430CC::COND_LO:
154    CC = MSP430CC::COND_HS;
155    break;
156  }
157
158  Cond[0].setImm(CC);
159  return false;
160}
161
162bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
163  const MCInstrDesc &MCID = MI->getDesc();
164  if (!MCID.isTerminator()) return false;
165
166  // Conditional branch is a special case.
167  if (MCID.isBranch() && !MCID.isBarrier())
168    return true;
169  if (!MCID.isPredicable())
170    return true;
171  return !isPredicated(MI);
172}
173
174bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
175                                    MachineBasicBlock *&TBB,
176                                    MachineBasicBlock *&FBB,
177                                    SmallVectorImpl<MachineOperand> &Cond,
178                                    bool AllowModify) const {
179  // Start from the bottom of the block and work up, examining the
180  // terminator instructions.
181  MachineBasicBlock::iterator I = MBB.end();
182  while (I != MBB.begin()) {
183    --I;
184    if (I->isDebugValue())
185      continue;
186
187    // Working from the bottom, when we see a non-terminator
188    // instruction, we're done.
189    if (!isUnpredicatedTerminator(I))
190      break;
191
192    // A terminator that isn't a branch can't easily be handled
193    // by this analysis.
194    if (!I->getDesc().isBranch())
195      return true;
196
197    // Cannot handle indirect branches.
198    if (I->getOpcode() == MSP430::Br ||
199        I->getOpcode() == MSP430::Bm)
200      return true;
201
202    // Handle unconditional branches.
203    if (I->getOpcode() == MSP430::JMP) {
204      if (!AllowModify) {
205        TBB = I->getOperand(0).getMBB();
206        continue;
207      }
208
209      // If the block has any instructions after a JMP, delete them.
210      while (llvm::next(I) != MBB.end())
211        llvm::next(I)->eraseFromParent();
212      Cond.clear();
213      FBB = 0;
214
215      // Delete the JMP if it's equivalent to a fall-through.
216      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
217        TBB = 0;
218        I->eraseFromParent();
219        I = MBB.end();
220        continue;
221      }
222
223      // TBB is used to indicate the unconditinal destination.
224      TBB = I->getOperand(0).getMBB();
225      continue;
226    }
227
228    // Handle conditional branches.
229    assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
230    MSP430CC::CondCodes BranchCode =
231      static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
232    if (BranchCode == MSP430CC::COND_INVALID)
233      return true;  // Can't handle weird stuff.
234
235    // Working from the bottom, handle the first conditional branch.
236    if (Cond.empty()) {
237      FBB = TBB;
238      TBB = I->getOperand(0).getMBB();
239      Cond.push_back(MachineOperand::CreateImm(BranchCode));
240      continue;
241    }
242
243    // Handle subsequent conditional branches. Only handle the case where all
244    // conditional branches branch to the same destination.
245    assert(Cond.size() == 1);
246    assert(TBB);
247
248    // Only handle the case where all conditional branches branch to
249    // the same destination.
250    if (TBB != I->getOperand(0).getMBB())
251      return true;
252
253    MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
254    // If the conditions are the same, we can leave them alone.
255    if (OldBranchCode == BranchCode)
256      continue;
257
258    return true;
259  }
260
261  return false;
262}
263
264unsigned
265MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
266                              MachineBasicBlock *FBB,
267                              const SmallVectorImpl<MachineOperand> &Cond,
268                              DebugLoc DL) const {
269  // Shouldn't be a fall through.
270  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
271  assert((Cond.size() == 1 || Cond.size() == 0) &&
272         "MSP430 branch conditions have one component!");
273
274  if (Cond.empty()) {
275    // Unconditional branch?
276    assert(!FBB && "Unconditional branch with multiple successors!");
277    BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
278    return 1;
279  }
280
281  // Conditional branch.
282  unsigned Count = 0;
283  BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
284  ++Count;
285
286  if (FBB) {
287    // Two-way Conditional branch. Insert the second branch.
288    BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
289    ++Count;
290  }
291  return Count;
292}
293
294/// GetInstSize - Return the number of bytes of code the specified
295/// instruction may be.  This returns the maximum number of bytes.
296///
297unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
298  const MCInstrDesc &Desc = MI->getDesc();
299
300  switch (Desc.TSFlags & MSP430II::SizeMask) {
301  default:
302    switch (Desc.getOpcode()) {
303    default:
304      assert(0 && "Unknown instruction size!");
305    case TargetOpcode::PROLOG_LABEL:
306    case TargetOpcode::EH_LABEL:
307    case TargetOpcode::IMPLICIT_DEF:
308    case TargetOpcode::KILL:
309    case TargetOpcode::DBG_VALUE:
310      return 0;
311    case TargetOpcode::INLINEASM: {
312      const MachineFunction *MF = MI->getParent()->getParent();
313      const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
314      return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
315                                    *MF->getTarget().getMCAsmInfo());
316    }
317    }
318  case MSP430II::SizeSpecial:
319    switch (MI->getOpcode()) {
320    default:
321      assert(0 && "Unknown instruction size!");
322    case MSP430::SAR8r1c:
323    case MSP430::SAR16r1c:
324      return 4;
325    }
326  case MSP430II::Size2Bytes:
327    return 2;
328  case MSP430II::Size4Bytes:
329    return 4;
330  case MSP430II::Size6Bytes:
331    return 6;
332  }
333
334  return 6;
335}
336