MSP430InstrInfo.cpp revision e837dead3c8dc3445ef6a0e2322179c57e264a13
1//===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MSP430 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MSP430.h" 15#include "MSP430InstrInfo.h" 16#include "MSP430MachineFunctionInfo.h" 17#include "MSP430TargetMachine.h" 18#include "MSP430GenInstrInfo.inc" 19#include "llvm/Function.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/PseudoSourceValue.h" 24#include "llvm/Support/ErrorHandling.h" 25 26using namespace llvm; 27 28MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm) 29 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)), 30 RI(tm, *this), TM(tm) {} 31 32void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 33 MachineBasicBlock::iterator MI, 34 unsigned SrcReg, bool isKill, int FrameIdx, 35 const TargetRegisterClass *RC, 36 const TargetRegisterInfo *TRI) const { 37 DebugLoc DL; 38 if (MI != MBB.end()) DL = MI->getDebugLoc(); 39 MachineFunction &MF = *MBB.getParent(); 40 MachineFrameInfo &MFI = *MF.getFrameInfo(); 41 42 MachineMemOperand *MMO = 43 MF.getMachineMemOperand( 44 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 45 MachineMemOperand::MOStore, 46 MFI.getObjectSize(FrameIdx), 47 MFI.getObjectAlignment(FrameIdx)); 48 49 if (RC == &MSP430::GR16RegClass) 50 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) 51 .addFrameIndex(FrameIdx).addImm(0) 52 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 53 else if (RC == &MSP430::GR8RegClass) 54 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) 55 .addFrameIndex(FrameIdx).addImm(0) 56 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 57 else 58 llvm_unreachable("Cannot store this register to stack slot!"); 59} 60 61void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MI, 63 unsigned DestReg, int FrameIdx, 64 const TargetRegisterClass *RC, 65 const TargetRegisterInfo *TRI) const{ 66 DebugLoc DL; 67 if (MI != MBB.end()) DL = MI->getDebugLoc(); 68 MachineFunction &MF = *MBB.getParent(); 69 MachineFrameInfo &MFI = *MF.getFrameInfo(); 70 71 MachineMemOperand *MMO = 72 MF.getMachineMemOperand( 73 MachinePointerInfo(PseudoSourceValue::getFixedStack(FrameIdx)), 74 MachineMemOperand::MOLoad, 75 MFI.getObjectSize(FrameIdx), 76 MFI.getObjectAlignment(FrameIdx)); 77 78 if (RC == &MSP430::GR16RegClass) 79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm)) 80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 81 else if (RC == &MSP430::GR8RegClass) 82 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm)) 83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); 84 else 85 llvm_unreachable("Cannot store this register to stack slot!"); 86} 87 88void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 89 MachineBasicBlock::iterator I, DebugLoc DL, 90 unsigned DestReg, unsigned SrcReg, 91 bool KillSrc) const { 92 unsigned Opc; 93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) 94 Opc = MSP430::MOV16rr; 95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) 96 Opc = MSP430::MOV8rr; 97 else 98 llvm_unreachable("Impossible reg-to-reg copy"); 99 100 BuildMI(MBB, I, DL, get(Opc), DestReg) 101 .addReg(SrcReg, getKillRegState(KillSrc)); 102} 103 104unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 105 MachineBasicBlock::iterator I = MBB.end(); 106 unsigned Count = 0; 107 108 while (I != MBB.begin()) { 109 --I; 110 if (I->isDebugValue()) 111 continue; 112 if (I->getOpcode() != MSP430::JMP && 113 I->getOpcode() != MSP430::JCC && 114 I->getOpcode() != MSP430::Br && 115 I->getOpcode() != MSP430::Bm) 116 break; 117 // Remove the branch. 118 I->eraseFromParent(); 119 I = MBB.end(); 120 ++Count; 121 } 122 123 return Count; 124} 125 126bool MSP430InstrInfo:: 127ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 128 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 129 130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 131 132 switch (CC) { 133 default: 134 assert(0 && "Invalid branch condition!"); 135 break; 136 case MSP430CC::COND_E: 137 CC = MSP430CC::COND_NE; 138 break; 139 case MSP430CC::COND_NE: 140 CC = MSP430CC::COND_E; 141 break; 142 case MSP430CC::COND_L: 143 CC = MSP430CC::COND_GE; 144 break; 145 case MSP430CC::COND_GE: 146 CC = MSP430CC::COND_L; 147 break; 148 case MSP430CC::COND_HS: 149 CC = MSP430CC::COND_LO; 150 break; 151 case MSP430CC::COND_LO: 152 CC = MSP430CC::COND_HS; 153 break; 154 } 155 156 Cond[0].setImm(CC); 157 return false; 158} 159 160bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 161 const MCInstrDesc &MCID = MI->getDesc(); 162 if (!MCID.isTerminator()) return false; 163 164 // Conditional branch is a special case. 165 if (MCID.isBranch() && !MCID.isBarrier()) 166 return true; 167 if (!MCID.isPredicable()) 168 return true; 169 return !isPredicated(MI); 170} 171 172bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 173 MachineBasicBlock *&TBB, 174 MachineBasicBlock *&FBB, 175 SmallVectorImpl<MachineOperand> &Cond, 176 bool AllowModify) const { 177 // Start from the bottom of the block and work up, examining the 178 // terminator instructions. 179 MachineBasicBlock::iterator I = MBB.end(); 180 while (I != MBB.begin()) { 181 --I; 182 if (I->isDebugValue()) 183 continue; 184 185 // Working from the bottom, when we see a non-terminator 186 // instruction, we're done. 187 if (!isUnpredicatedTerminator(I)) 188 break; 189 190 // A terminator that isn't a branch can't easily be handled 191 // by this analysis. 192 if (!I->getDesc().isBranch()) 193 return true; 194 195 // Cannot handle indirect branches. 196 if (I->getOpcode() == MSP430::Br || 197 I->getOpcode() == MSP430::Bm) 198 return true; 199 200 // Handle unconditional branches. 201 if (I->getOpcode() == MSP430::JMP) { 202 if (!AllowModify) { 203 TBB = I->getOperand(0).getMBB(); 204 continue; 205 } 206 207 // If the block has any instructions after a JMP, delete them. 208 while (llvm::next(I) != MBB.end()) 209 llvm::next(I)->eraseFromParent(); 210 Cond.clear(); 211 FBB = 0; 212 213 // Delete the JMP if it's equivalent to a fall-through. 214 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 215 TBB = 0; 216 I->eraseFromParent(); 217 I = MBB.end(); 218 continue; 219 } 220 221 // TBB is used to indicate the unconditinal destination. 222 TBB = I->getOperand(0).getMBB(); 223 continue; 224 } 225 226 // Handle conditional branches. 227 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch"); 228 MSP430CC::CondCodes BranchCode = 229 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); 230 if (BranchCode == MSP430CC::COND_INVALID) 231 return true; // Can't handle weird stuff. 232 233 // Working from the bottom, handle the first conditional branch. 234 if (Cond.empty()) { 235 FBB = TBB; 236 TBB = I->getOperand(0).getMBB(); 237 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 238 continue; 239 } 240 241 // Handle subsequent conditional branches. Only handle the case where all 242 // conditional branches branch to the same destination. 243 assert(Cond.size() == 1); 244 assert(TBB); 245 246 // Only handle the case where all conditional branches branch to 247 // the same destination. 248 if (TBB != I->getOperand(0).getMBB()) 249 return true; 250 251 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); 252 // If the conditions are the same, we can leave them alone. 253 if (OldBranchCode == BranchCode) 254 continue; 255 256 return true; 257 } 258 259 return false; 260} 261 262unsigned 263MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 264 MachineBasicBlock *FBB, 265 const SmallVectorImpl<MachineOperand> &Cond, 266 DebugLoc DL) const { 267 // Shouldn't be a fall through. 268 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 269 assert((Cond.size() == 1 || Cond.size() == 0) && 270 "MSP430 branch conditions have one component!"); 271 272 if (Cond.empty()) { 273 // Unconditional branch? 274 assert(!FBB && "Unconditional branch with multiple successors!"); 275 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB); 276 return 1; 277 } 278 279 // Conditional branch. 280 unsigned Count = 0; 281 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm()); 282 ++Count; 283 284 if (FBB) { 285 // Two-way Conditional branch. Insert the second branch. 286 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB); 287 ++Count; 288 } 289 return Count; 290} 291 292/// GetInstSize - Return the number of bytes of code the specified 293/// instruction may be. This returns the maximum number of bytes. 294/// 295unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 296 const MCInstrDesc &Desc = MI->getDesc(); 297 298 switch (Desc.TSFlags & MSP430II::SizeMask) { 299 default: 300 switch (Desc.getOpcode()) { 301 default: 302 assert(0 && "Unknown instruction size!"); 303 case TargetOpcode::PROLOG_LABEL: 304 case TargetOpcode::EH_LABEL: 305 case TargetOpcode::IMPLICIT_DEF: 306 case TargetOpcode::KILL: 307 case TargetOpcode::DBG_VALUE: 308 return 0; 309 case TargetOpcode::INLINEASM: { 310 const MachineFunction *MF = MI->getParent()->getParent(); 311 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 312 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(), 313 *MF->getTarget().getMCAsmInfo()); 314 } 315 } 316 case MSP430II::SizeSpecial: 317 switch (MI->getOpcode()) { 318 default: 319 assert(0 && "Unknown instruction size!"); 320 case MSP430::SAR8r1c: 321 case MSP430::SAR16r1c: 322 return 4; 323 } 324 case MSP430II::Size2Bytes: 325 return 2; 326 case MSP430II::Size4Bytes: 327 return 4; 328 case MSP430II::Size6Bytes: 329 return 6; 330 } 331 332 return 6; 333} 334