MSP430InstrInfo.h revision 746ad69e088176819981b4b2c5ac8dcd49f5e60e 
1//===- MSP430InstrInfo.h - MSP430 Instruction Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_MSP430INSTRINFO_H
15#define LLVM_TARGET_MSP430INSTRINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "MSP430RegisterInfo.h"
19
20namespace llvm {
21
22class MSP430TargetMachine;
23
24/// MSP430II - This namespace holds all of the target specific flags that
25/// instruction info tracks.
26///
27namespace MSP430II {
28  enum {
29    SizeShift   = 2,
30    SizeMask    = 7 << SizeShift,
31
32    SizeUnknown = 0 << SizeShift,
33    SizeSpecial = 1 << SizeShift,
34    Size2Bytes  = 2 << SizeShift,
35    Size4Bytes  = 3 << SizeShift,
36    Size6Bytes  = 4 << SizeShift
37  };
38}
39
40class MSP430InstrInfo : public TargetInstrInfoImpl {
41  const MSP430RegisterInfo RI;
42  MSP430TargetMachine &TM;
43public:
44  explicit MSP430InstrInfo(MSP430TargetMachine &TM);
45
46  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
47  /// such, whenever a client has an instance of instruction info, it should
48  /// always be able to get register info as well (through this method).
49  ///
50  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
51
52  bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53                    unsigned DestReg, unsigned SrcReg,
54                    const TargetRegisterClass *DestRC,
55                    const TargetRegisterClass *SrcRC) const;
56
57  bool isMoveInstr(const MachineInstr& MI,
58                   unsigned &SrcReg, unsigned &DstReg,
59                   unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
60
61  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
62                                   MachineBasicBlock::iterator MI,
63                                   unsigned SrcReg, bool isKill,
64                                   int FrameIndex,
65                                   const TargetRegisterClass *RC,
66                                   const TargetRegisterInfo *TRI) const;
67  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
68                                    MachineBasicBlock::iterator MI,
69                                    unsigned DestReg, int FrameIdx,
70                                    const TargetRegisterClass *RC,
71                                    const TargetRegisterInfo *TRI) const;
72
73  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
74                                         MachineBasicBlock::iterator MI,
75                                 const std::vector<CalleeSavedInfo> &CSI) const;
76  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
77                                           MachineBasicBlock::iterator MI,
78                                 const std::vector<CalleeSavedInfo> &CSI) const;
79
80  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
81
82  // Branch folding goodness
83  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
84  bool isUnpredicatedTerminator(const MachineInstr *MI) const;
85  bool AnalyzeBranch(MachineBasicBlock &MBB,
86                     MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
87                     SmallVectorImpl<MachineOperand> &Cond,
88                     bool AllowModify) const;
89
90  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
91  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
92                        MachineBasicBlock *FBB,
93                        const SmallVectorImpl<MachineOperand> &Cond) const;
94
95};
96
97}
98
99#endif
100