MSP430RegisterInfo.cpp revision 16c29b5f285f375be53dabaa73e3e91107485fe4 
1//===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-reg-info"
15
16#include "MSP430.h"
17#include "MSP430MachineFunctionInfo.h"
18#include "MSP430RegisterInfo.h"
19#include "MSP430TargetMachine.h"
20#include "llvm/Function.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/Target/TargetMachine.h"
25#include "llvm/Target/TargetOptions.h"
26#include "llvm/ADT/BitVector.h"
27#include "llvm/Support/ErrorHandling.h"
28
29using namespace llvm;
30
31// FIXME: Provide proper call frame setup / destroy opcodes.
32MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
33                                       const TargetInstrInfo &tii)
34  : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
35    TM(tm), TII(tii) {
36  StackAlign = TM.getFrameLowering()->getStackAlignment();
37}
38
39const unsigned*
40MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41  const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
42  const Function* F = MF->getFunction();
43  static const unsigned CalleeSavedRegs[] = {
44    MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
45    MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
46    0
47  };
48  static const unsigned CalleeSavedRegsFP[] = {
49    MSP430::R5W, MSP430::R6W, MSP430::R7W,
50    MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
51    0
52  };
53  static const unsigned CalleeSavedRegsIntr[] = {
54    MSP430::FPW,  MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
55    MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
56    MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
57    0
58  };
59  static const unsigned CalleeSavedRegsIntrFP[] = {
60    MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
61    MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
62    MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
63    0
64  };
65
66  if (TFI->hasFP(*MF))
67    return (F->getCallingConv() == CallingConv::MSP430_INTR ?
68            CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
69  else
70    return (F->getCallingConv() == CallingConv::MSP430_INTR ?
71            CalleeSavedRegsIntr : CalleeSavedRegs);
72
73}
74
75BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
76  BitVector Reserved(getNumRegs());
77  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
78
79  // Mark 4 special registers as reserved.
80  Reserved.set(MSP430::PCW);
81  Reserved.set(MSP430::SPW);
82  Reserved.set(MSP430::SRW);
83  Reserved.set(MSP430::CGW);
84
85  // Mark frame pointer as reserved if needed.
86  if (TFI->hasFP(MF))
87    Reserved.set(MSP430::FPW);
88
89  return Reserved;
90}
91
92const TargetRegisterClass *
93MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
94  return &MSP430::GR16RegClass;
95}
96
97void MSP430RegisterInfo::
98eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
99                              MachineBasicBlock::iterator I) const {
100  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
101
102  if (!TFI->hasReservedCallFrame(MF)) {
103    // If the stack pointer can be changed after prologue, turn the
104    // adjcallstackup instruction into a 'sub SPW, <amt>' and the
105    // adjcallstackdown instruction into 'add SPW, <amt>'
106    // TODO: consider using push / pop instead of sub + store / add
107    MachineInstr *Old = I;
108    uint64_t Amount = Old->getOperand(0).getImm();
109    if (Amount != 0) {
110      // We need to keep the stack aligned properly.  To do this, we round the
111      // amount of space needed for the outgoing arguments up to the next
112      // alignment boundary.
113      Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
114
115      MachineInstr *New = 0;
116      if (Old->getOpcode() == getCallFrameSetupOpcode()) {
117        New = BuildMI(MF, Old->getDebugLoc(),
118                      TII.get(MSP430::SUB16ri), MSP430::SPW)
119          .addReg(MSP430::SPW).addImm(Amount);
120      } else {
121        assert(Old->getOpcode() == getCallFrameDestroyOpcode());
122        // factor out the amount the callee already popped.
123        uint64_t CalleeAmt = Old->getOperand(1).getImm();
124        Amount -= CalleeAmt;
125        if (Amount)
126          New = BuildMI(MF, Old->getDebugLoc(),
127                        TII.get(MSP430::ADD16ri), MSP430::SPW)
128            .addReg(MSP430::SPW).addImm(Amount);
129      }
130
131      if (New) {
132        // The SRW implicit def is dead.
133        New->getOperand(3).setIsDead();
134
135        // Replace the pseudo instruction with a new instruction...
136        MBB.insert(I, New);
137      }
138    }
139  } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
140    // If we are performing frame pointer elimination and if the callee pops
141    // something off the stack pointer, add it back.
142    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
143      MachineInstr *Old = I;
144      MachineInstr *New =
145        BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
146                MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
147      // The SRW implicit def is dead.
148      New->getOperand(3).setIsDead();
149
150      MBB.insert(I, New);
151    }
152  }
153
154  MBB.erase(I);
155}
156
157void
158MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
159                                        int SPAdj, RegScavenger *RS) const {
160  assert(SPAdj == 0 && "Unexpected");
161
162  unsigned i = 0;
163  MachineInstr &MI = *II;
164  MachineBasicBlock &MBB = *MI.getParent();
165  MachineFunction &MF = *MBB.getParent();
166  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
167  DebugLoc dl = MI.getDebugLoc();
168  while (!MI.getOperand(i).isFI()) {
169    ++i;
170    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
171  }
172
173  int FrameIndex = MI.getOperand(i).getIndex();
174
175  unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
176  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
177
178  // Skip the saved PC
179  Offset += 2;
180
181  if (!TFI->hasFP(MF))
182    Offset += MF.getFrameInfo()->getStackSize();
183  else
184    Offset += 2; // Skip the saved FPW
185
186  // Fold imm into offset
187  Offset += MI.getOperand(i+1).getImm();
188
189  if (MI.getOpcode() == MSP430::ADD16ri) {
190    // This is actually "load effective address" of the stack slot
191    // instruction. We have only two-address instructions, thus we need to
192    // expand it into mov + add
193
194    MI.setDesc(TII.get(MSP430::MOV16rr));
195    MI.getOperand(i).ChangeToRegister(BasePtr, false);
196
197    if (Offset == 0)
198      return;
199
200    // We need to materialize the offset via add instruction.
201    unsigned DstReg = MI.getOperand(0).getReg();
202    if (Offset < 0)
203      BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
204        .addReg(DstReg).addImm(-Offset);
205    else
206      BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
207        .addReg(DstReg).addImm(Offset);
208
209    return;
210  }
211
212  MI.getOperand(i).ChangeToRegister(BasePtr, false);
213  MI.getOperand(i+1).ChangeToImmediate(Offset);
214}
215
216void
217MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
218                                                                         const {
219  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
220
221  // Create a frame entry for the FPW register that must be saved.
222  if (TFI->hasFP(MF)) {
223    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true);
224    (void)FrameIdx;
225    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
226           "Slot for FPW register must be last in order to be found!");
227  }
228}
229
230unsigned MSP430RegisterInfo::getRARegister() const {
231  return MSP430::PCW;
232}
233
234unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
235  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
236
237  return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
238}
239
240int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
241  llvm_unreachable("Not implemented yet!");
242  return 0;
243}
244
245#include "MSP430GenRegisterInfo.inc"
246