MSP430RegisterInfo.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-reg-info"
15
16#include "MSP430RegisterInfo.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Target/TargetMachine.h"
27#include "llvm/Target/TargetOptions.h"
28
29#define GET_REGINFO_TARGET_DESC
30#include "MSP430GenRegisterInfo.inc"
31
32using namespace llvm;
33
34// FIXME: Provide proper call frame setup / destroy opcodes.
35MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm)
36  : MSP430GenRegisterInfo(MSP430::PCW), TM(tm) {
37  StackAlign = TM.getFrameLowering()->getStackAlignment();
38}
39
40const uint16_t*
41MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
42  const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
43  const Function* F = MF->getFunction();
44  static const uint16_t CalleeSavedRegs[] = {
45    MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
46    MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
47    0
48  };
49  static const uint16_t CalleeSavedRegsFP[] = {
50    MSP430::R5W, MSP430::R6W, MSP430::R7W,
51    MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
52    0
53  };
54  static const uint16_t CalleeSavedRegsIntr[] = {
55    MSP430::FPW,  MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
56    MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
57    MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
58    0
59  };
60  static const uint16_t CalleeSavedRegsIntrFP[] = {
61    MSP430::R5W,  MSP430::R6W,  MSP430::R7W,
62    MSP430::R8W,  MSP430::R9W,  MSP430::R10W, MSP430::R11W,
63    MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
64    0
65  };
66
67  if (TFI->hasFP(*MF))
68    return (F->getCallingConv() == CallingConv::MSP430_INTR ?
69            CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
70  else
71    return (F->getCallingConv() == CallingConv::MSP430_INTR ?
72            CalleeSavedRegsIntr : CalleeSavedRegs);
73
74}
75
76BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
77  BitVector Reserved(getNumRegs());
78  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
79
80  // Mark 4 special registers with subregisters as reserved.
81  Reserved.set(MSP430::PCB);
82  Reserved.set(MSP430::SPB);
83  Reserved.set(MSP430::SRB);
84  Reserved.set(MSP430::CGB);
85  Reserved.set(MSP430::PCW);
86  Reserved.set(MSP430::SPW);
87  Reserved.set(MSP430::SRW);
88  Reserved.set(MSP430::CGW);
89
90  // Mark frame pointer as reserved if needed.
91  if (TFI->hasFP(MF)) {
92    Reserved.set(MSP430::FPB);
93    Reserved.set(MSP430::FPW);
94  }
95
96  return Reserved;
97}
98
99const TargetRegisterClass *
100MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
101                                                                         const {
102  return &MSP430::GR16RegClass;
103}
104
105void
106MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
107                                        int SPAdj, unsigned FIOperandNum,
108                                        RegScavenger *RS) const {
109  assert(SPAdj == 0 && "Unexpected");
110
111  MachineInstr &MI = *II;
112  MachineBasicBlock &MBB = *MI.getParent();
113  MachineFunction &MF = *MBB.getParent();
114  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
115  DebugLoc dl = MI.getDebugLoc();
116  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
117
118  unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
119  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
120
121  // Skip the saved PC
122  Offset += 2;
123
124  if (!TFI->hasFP(MF))
125    Offset += MF.getFrameInfo()->getStackSize();
126  else
127    Offset += 2; // Skip the saved FPW
128
129  // Fold imm into offset
130  Offset += MI.getOperand(FIOperandNum + 1).getImm();
131
132  if (MI.getOpcode() == MSP430::ADD16ri) {
133    // This is actually "load effective address" of the stack slot
134    // instruction. We have only two-address instructions, thus we need to
135    // expand it into mov + add
136    const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
137
138    MI.setDesc(TII.get(MSP430::MOV16rr));
139    MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
140
141    if (Offset == 0)
142      return;
143
144    // We need to materialize the offset via add instruction.
145    unsigned DstReg = MI.getOperand(0).getReg();
146    if (Offset < 0)
147      BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
148        .addReg(DstReg).addImm(-Offset);
149    else
150      BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
151        .addReg(DstReg).addImm(Offset);
152
153    return;
154  }
155
156  MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
157  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
158}
159
160unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
161  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
162
163  return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW;
164}
165