MSP430RegisterInfo.cpp revision 7896c9f436a4eda5ec15e882a7505ba482a2fcd0 
1//===- MSP430RegisterInfo.cpp - MSP430 Register Information ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-reg-info"
15
16#include "MSP430.h"
17#include "MSP430MachineFunctionInfo.h"
18#include "MSP430RegisterInfo.h"
19#include "MSP430TargetMachine.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/Target/TargetMachine.h"
24#include "llvm/Target/TargetOptions.h"
25#include "llvm/ADT/BitVector.h"
26#include "llvm/Support/ErrorHandling.h"
27
28using namespace llvm;
29
30// FIXME: Provide proper call frame setup / destroy opcodes.
31MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
32                                       const TargetInstrInfo &tii)
33  : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
34    TM(tm), TII(tii) {
35  StackAlign = TM.getFrameInfo()->getStackAlignment();
36}
37
38const unsigned*
39MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40  static const unsigned CalleeSavedRegs[] = {
41    MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
42    MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
43    0
44  };
45
46  return CalleeSavedRegs;
47}
48
49const TargetRegisterClass *const *
50MSP430RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
51  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
52    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
53    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
54    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
55    &MSP430::GR16RegClass, &MSP430::GR16RegClass,
56    0
57  };
58
59  return CalleeSavedRegClasses;
60}
61
62BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
63  BitVector Reserved(getNumRegs());
64
65  // Mark 4 special registers as reserved.
66  Reserved.set(MSP430::PCW);
67  Reserved.set(MSP430::SPW);
68  Reserved.set(MSP430::SRW);
69  Reserved.set(MSP430::CGW);
70
71  // Mark frame pointer as reserved if needed.
72  if (hasFP(MF))
73    Reserved.set(MSP430::FPW);
74
75  return Reserved;
76}
77
78const TargetRegisterClass *
79MSP430RegisterInfo::getPointerRegClass(unsigned Kind) const {
80  return &MSP430::GR16RegClass;
81}
82
83
84bool MSP430RegisterInfo::hasFP(const MachineFunction &MF) const {
85  return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
86}
87
88bool MSP430RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
89  return !MF.getFrameInfo()->hasVarSizedObjects();
90}
91
92void MSP430RegisterInfo::
93eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
94                              MachineBasicBlock::iterator I) const {
95  if (!hasReservedCallFrame(MF)) {
96    // If the stack pointer can be changed after prologue, turn the
97    // adjcallstackup instruction into a 'sub SPW, <amt>' and the
98    // adjcallstackdown instruction into 'add SPW, <amt>'
99    // TODO: consider using push / pop instead of sub + store / add
100    MachineInstr *Old = I;
101    uint64_t Amount = Old->getOperand(0).getImm();
102    if (Amount != 0) {
103      // We need to keep the stack aligned properly.  To do this, we round the
104      // amount of space needed for the outgoing arguments up to the next
105      // alignment boundary.
106      Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
107
108      MachineInstr *New = 0;
109      if (Old->getOpcode() == getCallFrameSetupOpcode()) {
110        New = BuildMI(MF, Old->getDebugLoc(),
111                      TII.get(MSP430::SUB16ri), MSP430::SPW)
112          .addReg(MSP430::SPW).addImm(Amount);
113      } else {
114        assert(Old->getOpcode() == getCallFrameDestroyOpcode());
115        // factor out the amount the callee already popped.
116        uint64_t CalleeAmt = Old->getOperand(1).getImm();
117        Amount -= CalleeAmt;
118        if (Amount)
119          New = BuildMI(MF, Old->getDebugLoc(),
120                        TII.get(MSP430::ADD16ri), MSP430::SPW)
121            .addReg(MSP430::SPW).addImm(Amount);
122      }
123
124      if (New) {
125        // The SRW implicit def is dead.
126        New->getOperand(3).setIsDead();
127
128        // Replace the pseudo instruction with a new instruction...
129        MBB.insert(I, New);
130      }
131    }
132  } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
133    // If we are performing frame pointer elimination and if the callee pops
134    // something off the stack pointer, add it back.
135    if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
136      MachineInstr *Old = I;
137      MachineInstr *New =
138        BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
139                MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
140      // The SRW implicit def is dead.
141      New->getOperand(3).setIsDead();
142
143      MBB.insert(I, New);
144    }
145  }
146
147  MBB.erase(I);
148}
149
150unsigned
151MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
152                                        int SPAdj, int *Value,
153                                        RegScavenger *RS) const {
154  assert(SPAdj == 0 && "Unexpected");
155
156  unsigned i = 0;
157  MachineInstr &MI = *II;
158  MachineBasicBlock &MBB = *MI.getParent();
159  MachineFunction &MF = *MBB.getParent();
160  DebugLoc dl = MI.getDebugLoc();
161  while (!MI.getOperand(i).isFI()) {
162    ++i;
163    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
164  }
165
166  int FrameIndex = MI.getOperand(i).getIndex();
167
168  unsigned BasePtr = (hasFP(MF) ? MSP430::FPW : MSP430::SPW);
169  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
170
171  // Skip the saved PC
172  Offset += 2;
173
174  if (!hasFP(MF))
175    Offset += MF.getFrameInfo()->getStackSize();
176  else
177    Offset += 2; // Skip the saved FPW
178
179  // Fold imm into offset
180  Offset += MI.getOperand(i+1).getImm();
181
182  if (MI.getOpcode() == MSP430::ADD16ri) {
183    // This is actually "load effective address" of the stack slot
184    // instruction. We have only two-address instructions, thus we need to
185    // expand it into mov + add
186
187    MI.setDesc(TII.get(MSP430::MOV16rr));
188    MI.getOperand(i).ChangeToRegister(BasePtr, false);
189
190    if (Offset == 0)
191      return 0;
192
193    // We need to materialize the offset via add instruction.
194    unsigned DstReg = MI.getOperand(0).getReg();
195    if (Offset < 0)
196      BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
197        .addReg(DstReg).addImm(-Offset);
198    else
199      BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
200        .addReg(DstReg).addImm(Offset);
201
202    return 0;
203  }
204
205  MI.getOperand(i).ChangeToRegister(BasePtr, false);
206  MI.getOperand(i+1).ChangeToImmediate(Offset);
207  return 0;
208}
209
210void
211MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
212                                                                         const {
213  // Create a frame entry for the FPW register that must be saved.
214  if (hasFP(MF)) {
215    int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true, false);
216    assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
217           "Slot for FPW register must be last in order to be found!");
218    FrameIdx = 0;
219  }
220}
221
222
223void MSP430RegisterInfo::emitPrologue(MachineFunction &MF) const {
224  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
225  MachineFrameInfo *MFI = MF.getFrameInfo();
226  MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
227  MachineBasicBlock::iterator MBBI = MBB.begin();
228  DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
229                 DebugLoc::getUnknownLoc());
230
231  // Get the number of bytes to allocate from the FrameInfo.
232  uint64_t StackSize = MFI->getStackSize();
233
234  uint64_t NumBytes = 0;
235  if (hasFP(MF)) {
236    // Calculate required stack adjustment
237    uint64_t FrameSize = StackSize - 2;
238    NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize();
239
240    // Get the offset of the stack slot for the EBP register... which is
241    // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
242    // Update the frame offset adjustment.
243    MFI->setOffsetAdjustment(-NumBytes);
244
245    // Save FPW into the appropriate stack slot...
246    BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
247      .addReg(MSP430::FPW, RegState::Kill);
248
249    // Update FPW with the new base value...
250    BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
251      .addReg(MSP430::SPW);
252
253    // Mark the FramePtr as live-in in every block except the entry.
254    for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
255         I != E; ++I)
256      I->addLiveIn(MSP430::FPW);
257
258  } else
259    NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize();
260
261  // Skip the callee-saved push instructions.
262  while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
263    ++MBBI;
264
265  if (MBBI != MBB.end())
266    DL = MBBI->getDebugLoc();
267
268  if (NumBytes) { // adjust stack pointer: SPW -= numbytes
269    // If there is an SUB16ri of SPW immediately before this instruction, merge
270    // the two.
271    //NumBytes -= mergeSPUpdates(MBB, MBBI, true);
272    // If there is an ADD16ri or SUB16ri of SPW immediately after this
273    // instruction, merge the two instructions.
274    // mergeSPUpdatesDown(MBB, MBBI, &NumBytes);
275
276    if (NumBytes) {
277      MachineInstr *MI =
278        BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
279        .addReg(MSP430::SPW).addImm(NumBytes);
280      // The SRW implicit def is dead.
281      MI->getOperand(3).setIsDead();
282    }
283  }
284}
285
286void MSP430RegisterInfo::emitEpilogue(MachineFunction &MF,
287                                      MachineBasicBlock &MBB) const {
288  const MachineFrameInfo *MFI = MF.getFrameInfo();
289  MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>();
290  MachineBasicBlock::iterator MBBI = prior(MBB.end());
291  unsigned RetOpcode = MBBI->getOpcode();
292  DebugLoc DL = MBBI->getDebugLoc();
293
294  switch (RetOpcode) {
295  case MSP430::RET: break;  // These are ok
296  default:
297    llvm_unreachable("Can only insert epilog into returning blocks");
298  }
299
300  // Get the number of bytes to allocate from the FrameInfo
301  uint64_t StackSize = MFI->getStackSize();
302  unsigned CSSize = MSP430FI->getCalleeSavedFrameSize();
303  uint64_t NumBytes = 0;
304
305  if (hasFP(MF)) {
306    // Calculate required stack adjustment
307    uint64_t FrameSize = StackSize - 2;
308    NumBytes = FrameSize - CSSize;
309
310    // pop FPW.
311    BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
312  } else
313    NumBytes = StackSize - CSSize;
314
315  // Skip the callee-saved pop instructions.
316  while (MBBI != MBB.begin()) {
317    MachineBasicBlock::iterator PI = prior(MBBI);
318    unsigned Opc = PI->getOpcode();
319    if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
320      break;
321    --MBBI;
322  }
323
324  DL = MBBI->getDebugLoc();
325
326  // If there is an ADD16ri or SUB16ri of SPW immediately before this
327  // instruction, merge the two instructions.
328  //if (NumBytes || MFI->hasVarSizedObjects())
329  //  mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
330
331  if (MFI->hasVarSizedObjects()) {
332    BuildMI(MBB, MBBI, DL,
333            TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
334    if (CSSize) {
335      MachineInstr *MI =
336        BuildMI(MBB, MBBI, DL,
337                TII.get(MSP430::SUB16ri), MSP430::SPW)
338        .addReg(MSP430::SPW).addImm(CSSize);
339      // The SRW implicit def is dead.
340      MI->getOperand(3).setIsDead();
341    }
342  } else {
343    // adjust stack pointer back: SPW += numbytes
344    if (NumBytes) {
345      MachineInstr *MI =
346        BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
347        .addReg(MSP430::SPW).addImm(NumBytes);
348      // The SRW implicit def is dead.
349      MI->getOperand(3).setIsDead();
350    }
351  }
352}
353
354unsigned MSP430RegisterInfo::getRARegister() const {
355  return MSP430::PCW;
356}
357
358unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
359  return hasFP(MF) ? MSP430::FPW : MSP430::SPW;
360}
361
362int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
363  llvm_unreachable("Not implemented yet!");
364  return 0;
365}
366
367#include "MSP430GenRegisterInfo.inc"
368