MSP430RegisterInfo.td revision cf9adf2cbb8298e83b53d7bee2ddab4c875cb3c5
1//===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MSP430 register file 12//===----------------------------------------------------------------------===// 13 14class MSP430Reg<bits<4> num, string n> : Register<n> { 15 field bits<4> Num = num; 16 let Namespace = "MSP430"; 17} 18 19class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs> 20 : RegisterWithSubRegs<n, subregs> { 21 field bits<4> Num = num; 22 let Namespace = "MSP430"; 23} 24 25//===----------------------------------------------------------------------===// 26// Registers 27//===----------------------------------------------------------------------===// 28 29def PCB : MSP430Reg<0, "r0">; 30def SPB : MSP430Reg<1, "r1">; 31def SRB : MSP430Reg<2, "r2">; 32def CGB : MSP430Reg<3, "r3">; 33def FPB : MSP430Reg<4, "r4">; 34def R5B : MSP430Reg<5, "r5">; 35def R6B : MSP430Reg<6, "r6">; 36def R7B : MSP430Reg<7, "r7">; 37def R8B : MSP430Reg<8, "r8">; 38def R9B : MSP430Reg<9, "r9">; 39def R10B : MSP430Reg<10, "r10">; 40def R11B : MSP430Reg<11, "r11">; 41def R12B : MSP430Reg<12, "r12">; 42def R13B : MSP430Reg<13, "r13">; 43def R14B : MSP430Reg<14, "r14">; 44def R15B : MSP430Reg<15, "r15">; 45 46def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; 47def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>; 48def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>; 49def CGW : MSP430RegWithSubregs<3, "r3", [CGB]>; 50def FPW : MSP430RegWithSubregs<4, "r4", [FPB]>; 51def R5W : MSP430RegWithSubregs<5, "r5", [R5B]>; 52def R6W : MSP430RegWithSubregs<6, "r6", [R6B]>; 53def R7W : MSP430RegWithSubregs<7, "r7", [R7B]>; 54def R8W : MSP430RegWithSubregs<8, "r8", [R8B]>; 55def R9W : MSP430RegWithSubregs<9, "r9", [R9B]>; 56def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>; 57def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>; 58def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>; 59def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>; 60def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>; 61def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>; 62 63def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW, 64 R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], 65 [PCB, SPB, SRB, CGB, FPB, 66 R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; 67 68def GR8 : RegisterClass<"MSP430", [i8], 8, 69 // Volatile registers 70 [R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, 71 // Frame pointer, sometimes allocable 72 FPB, 73 // Volatile, but not allocable 74 PCB, SPB, SRB, CGB]> 75{ 76 let MethodProtos = [{ 77 iterator allocation_order_end(const MachineFunction &MF) const; 78 }]; 79 let MethodBodies = [{ 80 GR8Class::iterator 81 GR8Class::allocation_order_end(const MachineFunction &MF) const { 82 const TargetMachine &TM = MF.getTarget(); 83 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 84 // Depending on whether the function uses frame pointer or not, last 5 or 4 85 // registers on the list above are reserved 86 if (RI->hasFP(MF)) 87 return end()-5; 88 else 89 return end()-4; 90 } 91 }]; 92} 93 94def GR16 : RegisterClass<"MSP430", [i16], 16, 95 // Volatile registers 96 [R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W, 97 // Frame pointer, sometimes allocable 98 FPW, 99 // Volatile, but not allocable 100 PCW, SPW, SRW, CGW]> 101{ 102 let SubRegClassList = [GR8]; 103 let MethodProtos = [{ 104 iterator allocation_order_end(const MachineFunction &MF) const; 105 }]; 106 let MethodBodies = [{ 107 GR16Class::iterator 108 GR16Class::allocation_order_end(const MachineFunction &MF) const { 109 const TargetMachine &TM = MF.getTarget(); 110 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 111 // Depending on whether the function uses frame pointer or not, last 5 or 4 112 // registers on the list above are reserved 113 if (RI->hasFP(MF)) 114 return end()-5; 115 else 116 return end()-4; 117 } 118 }]; 119} 120 121