MipsAsmParser.cpp revision 5d637d7e93c1f6058c16b41b8ac7dd36c61b4a5c 
1//===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/MipsMCTargetDesc.h"
11#include "llvm/MC/MCParser/MCAsmLexer.h"
12#include "llvm/MC/MCTargetAsmParser.h"
13#include "llvm/Support/TargetRegistry.h"
14#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15#include "llvm/MC/MCTargetAsmParser.h"
16#include "llvm/MC/MCInst.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/Support/MathExtras.h"
19
20using namespace llvm;
21
22namespace {
23class MipsAsmParser : public MCTargetAsmParser {
24
25#define GET_ASSEMBLER_HEADER
26#include "MipsGenAsmMatcher.inc"
27
28  bool MatchAndEmitInstruction(SMLoc IDLoc,
29                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
30                               MCStreamer &Out);
31
32  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
33
34  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
35                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
36
37  bool ParseDirective(AsmToken DirectiveID);
38
39  OperandMatchResultTy parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
40
41  unsigned getMCInstOperandNum(unsigned Kind, MCInst &Inst,
42                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
43                               unsigned OperandNum, unsigned &NumMCOperands);
44
45public:
46  MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
47    : MCTargetAsmParser() {
48  }
49
50};
51}
52
53namespace {
54
55/// MipsOperand - Instances of this class represent a parsed Mips machine
56/// instruction.
57class MipsOperand : public MCParsedAsmOperand {
58  enum KindTy {
59    k_CondCode,
60    k_CoprocNum,
61    k_Immediate,
62    k_Memory,
63    k_PostIndexRegister,
64    k_Register,
65    k_Token
66  } Kind;
67
68  MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
69public:
70  void addRegOperands(MCInst &Inst, unsigned N) const {
71    llvm_unreachable("unimplemented!");
72  }
73  void addExpr(MCInst &Inst, const MCExpr *Expr) const{
74    llvm_unreachable("unimplemented!");
75  }
76  void addImmOperands(MCInst &Inst, unsigned N) const {
77    llvm_unreachable("unimplemented!");
78  }
79  void addMemOperands(MCInst &Inst, unsigned N) const {
80    llvm_unreachable("unimplemented!");
81  }
82
83  bool isReg() const { return Kind == k_Register; }
84  bool isImm() const { return Kind == k_Immediate; }
85  bool isToken() const { return Kind == k_Token; }
86  bool isMem() const { return Kind == k_Memory; }
87
88  StringRef getToken() const {
89    assert(Kind == k_Token && "Invalid access!");
90    return "";
91  }
92
93  unsigned getReg() const {
94    assert((Kind == k_Register) && "Invalid access!");
95    return 0;
96  }
97
98  virtual void print(raw_ostream &OS) const {
99    llvm_unreachable("unimplemented!");
100  }
101};
102}
103
104unsigned MipsAsmParser::
105getMCInstOperandNum(unsigned Kind, MCInst &Inst,
106                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
107                    unsigned OperandNum, unsigned &NumMCOperands) {
108  assert (0 && "getMCInstOperandNum() not supported by the Mips target.");
109  // The Mips backend doesn't currently include the matcher implementation, so
110  // the getMCInstOperandNumImpl() is undefined.  This is a temporary
111  // work around.
112  NumMCOperands = 0;
113  return 0;
114}
115
116bool MipsAsmParser::
117MatchAndEmitInstruction(SMLoc IDLoc,
118                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
119                        MCStreamer &Out) {
120  return true;
121}
122
123bool MipsAsmParser::
124ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
125  return true;
126}
127
128bool MipsAsmParser::
129ParseInstruction(StringRef Name, SMLoc NameLoc,
130                 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
131  return true;
132}
133
134bool MipsAsmParser::
135ParseDirective(AsmToken DirectiveID) {
136  return true;
137}
138
139MipsAsmParser::OperandMatchResultTy MipsAsmParser::
140  parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&) {
141  return MatchOperand_ParseFail;
142}
143
144extern "C" void LLVMInitializeMipsAsmParser() {
145  RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
146  RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
147  RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
148  RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
149}
150