MipsDisassembler.cpp revision 9fa81ab83898314d1a6608e8303dc57253292796 
1//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the Mips Disassembler.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips.h"
15#include "MipsRegisterInfo.h"
16#include "MipsSubtarget.h"
17#include "llvm/MC/MCDisassembler.h"
18#include "llvm/MC/MCFixedLenDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/Support/MathExtras.h"
22#include "llvm/Support/MemoryObject.h"
23#include "llvm/Support/TargetRegistry.h"
24
25using namespace llvm;
26
27typedef MCDisassembler::DecodeStatus DecodeStatus;
28
29namespace {
30
31/// MipsDisassemblerBase - a disasembler class for Mips.
32class MipsDisassemblerBase : public MCDisassembler {
33public:
34  /// Constructor     - Initializes the disassembler.
35  ///
36  MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
37                       bool bigEndian) :
38    MCDisassembler(STI), RegInfo(Info),
39    IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
40
41  virtual ~MipsDisassemblerBase() {}
42
43  const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
44
45  bool isN64() const { return IsN64; }
46
47private:
48  OwningPtr<const MCRegisterInfo> RegInfo;
49  bool IsN64;
50protected:
51  bool isBigEndian;
52};
53
54/// MipsDisassembler - a disasembler class for Mips32.
55class MipsDisassembler : public MipsDisassemblerBase {
56  bool IsMicroMips;
57public:
58  /// Constructor     - Initializes the disassembler.
59  ///
60  MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
61                   bool bigEndian) :
62    MipsDisassemblerBase(STI, Info, bigEndian) {
63      IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
64    }
65
66  /// getInstruction - See MCDisassembler.
67  virtual DecodeStatus getInstruction(MCInst &instr,
68                                      uint64_t &size,
69                                      const MemoryObject &region,
70                                      uint64_t address,
71                                      raw_ostream &vStream,
72                                      raw_ostream &cStream) const;
73};
74
75
76/// Mips64Disassembler - a disasembler class for Mips64.
77class Mips64Disassembler : public MipsDisassemblerBase {
78public:
79  /// Constructor     - Initializes the disassembler.
80  ///
81  Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
82                     bool bigEndian) :
83    MipsDisassemblerBase(STI, Info, bigEndian) {}
84
85  /// getInstruction - See MCDisassembler.
86  virtual DecodeStatus getInstruction(MCInst &instr,
87                                      uint64_t &size,
88                                      const MemoryObject &region,
89                                      uint64_t address,
90                                      raw_ostream &vStream,
91                                      raw_ostream &cStream) const;
92};
93
94} // end anonymous namespace
95
96// Forward declare these because the autogenerated code will reference them.
97// Definitions are further down.
98static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
99                                             unsigned RegNo,
100                                             uint64_t Address,
101                                             const void *Decoder);
102
103static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
104                                                 unsigned RegNo,
105                                                 uint64_t Address,
106                                                 const void *Decoder);
107
108static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
109                                             unsigned RegNo,
110                                             uint64_t Address,
111                                             const void *Decoder);
112
113static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
114                                           unsigned Insn,
115                                           uint64_t Address,
116                                           const void *Decoder);
117
118static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
119                                            unsigned RegNo,
120                                            uint64_t Address,
121                                            const void *Decoder);
122
123static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
124                                             unsigned RegNo,
125                                             uint64_t Address,
126                                             const void *Decoder);
127
128static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
129                                             unsigned RegNo,
130                                             uint64_t Address,
131                                             const void *Decoder);
132
133static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
134                                              unsigned RegNo,
135                                              uint64_t Address,
136                                              const void *Decoder);
137
138static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
139                                           unsigned RegNo,
140                                           uint64_t Address,
141                                           const void *Decoder);
142
143static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
144                                           unsigned RegNo,
145                                           uint64_t Address,
146                                           const void *Decoder);
147
148static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
149                                              unsigned Insn,
150                                              uint64_t Address,
151                                              const void *Decoder);
152
153static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
154                                              unsigned RegNo,
155                                              uint64_t Address,
156                                              const void *Decoder);
157
158static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
159                                                unsigned RegNo,
160                                                uint64_t Address,
161                                                const void *Decoder);
162
163static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
164                                               unsigned RegNo,
165                                               uint64_t Address,
166                                               const void *Decoder);
167
168static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
169                                               unsigned RegNo,
170                                               uint64_t Address,
171                                               const void *Decoder);
172
173static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
174                                               unsigned RegNo,
175                                               uint64_t Address,
176                                               const void *Decoder);
177
178static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
179                                               unsigned RegNo,
180                                               uint64_t Address,
181                                               const void *Decoder);
182
183static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
184                                               unsigned RegNo,
185                                               uint64_t Address,
186                                               const void *Decoder);
187
188static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
189                                               unsigned RegNo,
190                                               uint64_t Address,
191                                               const void *Decoder);
192
193static DecodeStatus DecodeBranchTarget(MCInst &Inst,
194                                       unsigned Offset,
195                                       uint64_t Address,
196                                       const void *Decoder);
197
198static DecodeStatus DecodeJumpTarget(MCInst &Inst,
199                                     unsigned Insn,
200                                     uint64_t Address,
201                                     const void *Decoder);
202
203static DecodeStatus DecodeMem(MCInst &Inst,
204                              unsigned Insn,
205                              uint64_t Address,
206                              const void *Decoder);
207
208static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
209                                     unsigned Insn,
210                                     uint64_t Address,
211                                     const void *Decoder);
212
213static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
214                                     unsigned Insn,
215                                     uint64_t Address,
216                                     const void *Decoder);
217
218static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
219                               uint64_t Address,
220                               const void *Decoder);
221
222static DecodeStatus DecodeSimm16(MCInst &Inst,
223                                 unsigned Insn,
224                                 uint64_t Address,
225                                 const void *Decoder);
226
227static DecodeStatus DecodeInsSize(MCInst &Inst,
228                                  unsigned Insn,
229                                  uint64_t Address,
230                                  const void *Decoder);
231
232static DecodeStatus DecodeExtSize(MCInst &Inst,
233                                  unsigned Insn,
234                                  uint64_t Address,
235                                  const void *Decoder);
236
237namespace llvm {
238extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
239              TheMips64elTarget;
240}
241
242static MCDisassembler *createMipsDisassembler(
243                       const Target &T,
244                       const MCSubtargetInfo &STI) {
245  return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
246}
247
248static MCDisassembler *createMipselDisassembler(
249                       const Target &T,
250                       const MCSubtargetInfo &STI) {
251  return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
252}
253
254static MCDisassembler *createMips64Disassembler(
255                       const Target &T,
256                       const MCSubtargetInfo &STI) {
257  return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
258}
259
260static MCDisassembler *createMips64elDisassembler(
261                       const Target &T,
262                       const MCSubtargetInfo &STI) {
263  return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
264}
265
266extern "C" void LLVMInitializeMipsDisassembler() {
267  // Register the disassembler.
268  TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
269                                         createMipsDisassembler);
270  TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
271                                         createMipselDisassembler);
272  TargetRegistry::RegisterMCDisassembler(TheMips64Target,
273                                         createMips64Disassembler);
274  TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
275                                         createMips64elDisassembler);
276}
277
278
279#include "MipsGenDisassemblerTables.inc"
280
281  /// readInstruction - read four bytes from the MemoryObject
282  /// and return 32 bit word sorted according to the given endianess
283static DecodeStatus readInstruction32(const MemoryObject &region,
284                                      uint64_t address,
285                                      uint64_t &size,
286                                      uint32_t &insn,
287                                      bool isBigEndian,
288                                      bool IsMicroMips) {
289  uint8_t Bytes[4];
290
291  // We want to read exactly 4 Bytes of data.
292  if (region.readBytes(address, 4, Bytes) == -1) {
293    size = 0;
294    return MCDisassembler::Fail;
295  }
296
297  if (isBigEndian) {
298    // Encoded as a big-endian 32-bit word in the stream.
299    insn = (Bytes[3] <<  0) |
300           (Bytes[2] <<  8) |
301           (Bytes[1] << 16) |
302           (Bytes[0] << 24);
303  }
304  else {
305    // Encoded as a small-endian 32-bit word in the stream.
306    // Little-endian byte ordering:
307    //   mips32r2:   4 | 3 | 2 | 1
308    //   microMIPS:  2 | 1 | 4 | 3
309    if (IsMicroMips) {
310      insn = (Bytes[2] <<  0) |
311             (Bytes[3] <<  8) |
312             (Bytes[0] << 16) |
313             (Bytes[1] << 24);
314    } else {
315      insn = (Bytes[0] <<  0) |
316             (Bytes[1] <<  8) |
317             (Bytes[2] << 16) |
318             (Bytes[3] << 24);
319    }
320  }
321
322  return MCDisassembler::Success;
323}
324
325DecodeStatus
326MipsDisassembler::getInstruction(MCInst &instr,
327                                 uint64_t &Size,
328                                 const MemoryObject &Region,
329                                 uint64_t Address,
330                                 raw_ostream &vStream,
331                                 raw_ostream &cStream) const {
332  uint32_t Insn;
333
334  DecodeStatus Result = readInstruction32(Region, Address, Size,
335                                          Insn, isBigEndian, IsMicroMips);
336  if (Result == MCDisassembler::Fail)
337    return MCDisassembler::Fail;
338
339  if (IsMicroMips) {
340    // Calling the auto-generated decoder function.
341    Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
342                               this, STI);
343    if (Result != MCDisassembler::Fail) {
344      Size = 4;
345      return Result;
346    }
347    return MCDisassembler::Fail;
348  }
349
350  // Calling the auto-generated decoder function.
351  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
352                             this, STI);
353  if (Result != MCDisassembler::Fail) {
354    Size = 4;
355    return Result;
356  }
357
358  return MCDisassembler::Fail;
359}
360
361DecodeStatus
362Mips64Disassembler::getInstruction(MCInst &instr,
363                                   uint64_t &Size,
364                                   const MemoryObject &Region,
365                                   uint64_t Address,
366                                   raw_ostream &vStream,
367                                   raw_ostream &cStream) const {
368  uint32_t Insn;
369
370  DecodeStatus Result = readInstruction32(Region, Address, Size,
371                                          Insn, isBigEndian, false);
372  if (Result == MCDisassembler::Fail)
373    return MCDisassembler::Fail;
374
375  // Calling the auto-generated decoder function.
376  Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
377                             this, STI);
378  if (Result != MCDisassembler::Fail) {
379    Size = 4;
380    return Result;
381  }
382  // If we fail to decode in Mips64 decoder space we can try in Mips32
383  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
384                             this, STI);
385  if (Result != MCDisassembler::Fail) {
386    Size = 4;
387    return Result;
388  }
389
390  return MCDisassembler::Fail;
391}
392
393static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
394  const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
395  return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
396}
397
398static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
399                                                 unsigned RegNo,
400                                                 uint64_t Address,
401                                                 const void *Decoder) {
402
403  return MCDisassembler::Fail;
404
405}
406
407static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
408                                             unsigned RegNo,
409                                             uint64_t Address,
410                                             const void *Decoder) {
411
412  if (RegNo > 31)
413    return MCDisassembler::Fail;
414
415  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
416  Inst.addOperand(MCOperand::CreateReg(Reg));
417  return MCDisassembler::Success;
418}
419
420static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
421                                             unsigned RegNo,
422                                             uint64_t Address,
423                                             const void *Decoder) {
424  if (RegNo > 31)
425    return MCDisassembler::Fail;
426  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
427  Inst.addOperand(MCOperand::CreateReg(Reg));
428  return MCDisassembler::Success;
429}
430
431static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
432                                           unsigned RegNo,
433                                           uint64_t Address,
434                                           const void *Decoder) {
435  if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
436    return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
437
438  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
439}
440
441static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
442                                            unsigned RegNo,
443                                            uint64_t Address,
444                                            const void *Decoder) {
445  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
446}
447
448static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
449                                             unsigned RegNo,
450                                             uint64_t Address,
451                                             const void *Decoder) {
452  if (RegNo > 31)
453    return MCDisassembler::Fail;
454
455  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
456  Inst.addOperand(MCOperand::CreateReg(Reg));
457  return MCDisassembler::Success;
458}
459
460static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
461                                             unsigned RegNo,
462                                             uint64_t Address,
463                                             const void *Decoder) {
464  if (RegNo > 31)
465    return MCDisassembler::Fail;
466
467  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
468  Inst.addOperand(MCOperand::CreateReg(Reg));
469  return MCDisassembler::Success;
470}
471
472static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
473                                              unsigned RegNo,
474                                              uint64_t Address,
475                                              const void *Decoder) {
476  if (RegNo > 31)
477    return MCDisassembler::Fail;
478
479  unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
480  Inst.addOperand(MCOperand::CreateReg(Reg));
481  return MCDisassembler::Success;
482}
483
484static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
485                                           unsigned RegNo,
486                                           uint64_t Address,
487                                           const void *Decoder) {
488  if (RegNo > 31)
489    return MCDisassembler::Fail;
490  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
491  Inst.addOperand(MCOperand::CreateReg(Reg));
492  return MCDisassembler::Success;
493}
494
495static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
496                                           unsigned RegNo,
497                                           uint64_t Address,
498                                           const void *Decoder) {
499  if (RegNo > 7)
500    return MCDisassembler::Fail;
501  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
502  Inst.addOperand(MCOperand::CreateReg(Reg));
503  return MCDisassembler::Success;
504}
505
506static DecodeStatus DecodeMem(MCInst &Inst,
507                              unsigned Insn,
508                              uint64_t Address,
509                              const void *Decoder) {
510  int Offset = SignExtend32<16>(Insn & 0xffff);
511  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
512  unsigned Base = fieldFromInstruction(Insn, 21, 5);
513
514  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
515  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
516
517  if(Inst.getOpcode() == Mips::SC){
518    Inst.addOperand(MCOperand::CreateReg(Reg));
519  }
520
521  Inst.addOperand(MCOperand::CreateReg(Reg));
522  Inst.addOperand(MCOperand::CreateReg(Base));
523  Inst.addOperand(MCOperand::CreateImm(Offset));
524
525  return MCDisassembler::Success;
526}
527
528static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
529                                     unsigned Insn,
530                                     uint64_t Address,
531                                     const void *Decoder) {
532  int Offset = SignExtend32<12>(Insn & 0x0fff);
533  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
534  unsigned Base = fieldFromInstruction(Insn, 16, 5);
535
536  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
537  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
538
539  Inst.addOperand(MCOperand::CreateReg(Reg));
540  Inst.addOperand(MCOperand::CreateReg(Base));
541  Inst.addOperand(MCOperand::CreateImm(Offset));
542
543  return MCDisassembler::Success;
544}
545
546static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
547                                     unsigned Insn,
548                                     uint64_t Address,
549                                     const void *Decoder) {
550  int Offset = SignExtend32<16>(Insn & 0xffff);
551  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
552  unsigned Base = fieldFromInstruction(Insn, 16, 5);
553
554  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
555  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
556
557  Inst.addOperand(MCOperand::CreateReg(Reg));
558  Inst.addOperand(MCOperand::CreateReg(Base));
559  Inst.addOperand(MCOperand::CreateImm(Offset));
560
561  return MCDisassembler::Success;
562}
563
564static DecodeStatus DecodeFMem(MCInst &Inst,
565                               unsigned Insn,
566                               uint64_t Address,
567                               const void *Decoder) {
568  int Offset = SignExtend32<16>(Insn & 0xffff);
569  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
570  unsigned Base = fieldFromInstruction(Insn, 21, 5);
571
572  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
573  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
574
575  Inst.addOperand(MCOperand::CreateReg(Reg));
576  Inst.addOperand(MCOperand::CreateReg(Base));
577  Inst.addOperand(MCOperand::CreateImm(Offset));
578
579  return MCDisassembler::Success;
580}
581
582
583static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
584                                              unsigned RegNo,
585                                              uint64_t Address,
586                                              const void *Decoder) {
587  // Currently only hardware register 29 is supported.
588  if (RegNo != 29)
589    return  MCDisassembler::Fail;
590  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
591  return MCDisassembler::Success;
592}
593
594static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
595                                              unsigned RegNo,
596                                              uint64_t Address,
597                                              const void *Decoder) {
598  if (RegNo > 30 || RegNo %2)
599    return MCDisassembler::Fail;
600
601  ;
602  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
603  Inst.addOperand(MCOperand::CreateReg(Reg));
604  return MCDisassembler::Success;
605}
606
607static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
608                                                unsigned RegNo,
609                                                uint64_t Address,
610                                                const void *Decoder) {
611  if (RegNo >= 4)
612    return MCDisassembler::Fail;
613
614  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
615  Inst.addOperand(MCOperand::CreateReg(Reg));
616  return MCDisassembler::Success;
617}
618
619static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
620                                               unsigned RegNo,
621                                               uint64_t Address,
622                                               const void *Decoder) {
623  if (RegNo >= 4)
624    return MCDisassembler::Fail;
625
626  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
627  Inst.addOperand(MCOperand::CreateReg(Reg));
628  return MCDisassembler::Success;
629}
630
631static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
632                                               unsigned RegNo,
633                                               uint64_t Address,
634                                               const void *Decoder) {
635  if (RegNo >= 4)
636    return MCDisassembler::Fail;
637
638  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
639  Inst.addOperand(MCOperand::CreateReg(Reg));
640  return MCDisassembler::Success;
641}
642
643static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
644                                               unsigned RegNo,
645                                               uint64_t Address,
646                                               const void *Decoder) {
647  if (RegNo > 31)
648    return MCDisassembler::Fail;
649
650  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
651  Inst.addOperand(MCOperand::CreateReg(Reg));
652  return MCDisassembler::Success;
653}
654
655static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
656                                               unsigned RegNo,
657                                               uint64_t Address,
658                                               const void *Decoder) {
659  if (RegNo > 31)
660    return MCDisassembler::Fail;
661
662  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
663  Inst.addOperand(MCOperand::CreateReg(Reg));
664  return MCDisassembler::Success;
665}
666
667static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
668                                               unsigned RegNo,
669                                               uint64_t Address,
670                                               const void *Decoder) {
671  if (RegNo > 31)
672    return MCDisassembler::Fail;
673
674  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
675  Inst.addOperand(MCOperand::CreateReg(Reg));
676  return MCDisassembler::Success;
677}
678
679static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
680                                               unsigned RegNo,
681                                               uint64_t Address,
682                                               const void *Decoder) {
683  if (RegNo > 31)
684    return MCDisassembler::Fail;
685
686  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
687  Inst.addOperand(MCOperand::CreateReg(Reg));
688  return MCDisassembler::Success;
689}
690
691static DecodeStatus DecodeBranchTarget(MCInst &Inst,
692                                       unsigned Offset,
693                                       uint64_t Address,
694                                       const void *Decoder) {
695  unsigned BranchOffset = Offset & 0xffff;
696  BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
697  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
698  return MCDisassembler::Success;
699}
700
701static DecodeStatus DecodeJumpTarget(MCInst &Inst,
702                                     unsigned Insn,
703                                     uint64_t Address,
704                                     const void *Decoder) {
705
706  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
707  Inst.addOperand(MCOperand::CreateImm(JumpOffset));
708  return MCDisassembler::Success;
709}
710
711
712static DecodeStatus DecodeSimm16(MCInst &Inst,
713                                 unsigned Insn,
714                                 uint64_t Address,
715                                 const void *Decoder) {
716  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
717  return MCDisassembler::Success;
718}
719
720static DecodeStatus DecodeInsSize(MCInst &Inst,
721                                  unsigned Insn,
722                                  uint64_t Address,
723                                  const void *Decoder) {
724  // First we need to grab the pos(lsb) from MCInst.
725  int Pos = Inst.getOperand(2).getImm();
726  int Size = (int) Insn - Pos + 1;
727  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
728  return MCDisassembler::Success;
729}
730
731static DecodeStatus DecodeExtSize(MCInst &Inst,
732                                  unsigned Insn,
733                                  uint64_t Address,
734                                  const void *Decoder) {
735  int Size = (int) Insn  + 1;
736  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
737  return MCDisassembler::Success;
738}
739