MipsDisassembler.cpp revision a674463aac1d0b5d039da11045ccfab5e849b886 
1//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the Mips Disassembler.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips.h"
15#include "MipsRegisterInfo.h"
16#include "MipsSubtarget.h"
17#include "llvm/MC/MCDisassembler.h"
18#include "llvm/MC/MCFixedLenDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/Support/MathExtras.h"
22#include "llvm/Support/MemoryObject.h"
23#include "llvm/Support/TargetRegistry.h"
24
25using namespace llvm;
26
27typedef MCDisassembler::DecodeStatus DecodeStatus;
28
29namespace {
30
31/// MipsDisassemblerBase - a disasembler class for Mips.
32class MipsDisassemblerBase : public MCDisassembler {
33public:
34  /// Constructor     - Initializes the disassembler.
35  ///
36  MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
37                       bool bigEndian) :
38    MCDisassembler(STI), RegInfo(Info),
39    IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
40
41  virtual ~MipsDisassemblerBase() {}
42
43  const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
44
45  bool isN64() const { return IsN64; }
46
47private:
48  OwningPtr<const MCRegisterInfo> RegInfo;
49  bool IsN64;
50protected:
51  bool isBigEndian;
52};
53
54/// MipsDisassembler - a disasembler class for Mips32.
55class MipsDisassembler : public MipsDisassemblerBase {
56  bool IsMicroMips;
57public:
58  /// Constructor     - Initializes the disassembler.
59  ///
60  MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
61                   bool bigEndian) :
62    MipsDisassemblerBase(STI, Info, bigEndian) {
63      IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
64    }
65
66  /// getInstruction - See MCDisassembler.
67  virtual DecodeStatus getInstruction(MCInst &instr,
68                                      uint64_t &size,
69                                      const MemoryObject &region,
70                                      uint64_t address,
71                                      raw_ostream &vStream,
72                                      raw_ostream &cStream) const;
73};
74
75
76/// Mips64Disassembler - a disasembler class for Mips64.
77class Mips64Disassembler : public MipsDisassemblerBase {
78public:
79  /// Constructor     - Initializes the disassembler.
80  ///
81  Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
82                     bool bigEndian) :
83    MipsDisassemblerBase(STI, Info, bigEndian) {}
84
85  /// getInstruction - See MCDisassembler.
86  virtual DecodeStatus getInstruction(MCInst &instr,
87                                      uint64_t &size,
88                                      const MemoryObject &region,
89                                      uint64_t address,
90                                      raw_ostream &vStream,
91                                      raw_ostream &cStream) const;
92};
93
94} // end anonymous namespace
95
96// Forward declare these because the autogenerated code will reference them.
97// Definitions are further down.
98static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
99                                             unsigned RegNo,
100                                             uint64_t Address,
101                                             const void *Decoder);
102
103static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
104                                                 unsigned RegNo,
105                                                 uint64_t Address,
106                                                 const void *Decoder);
107
108static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
109                                             unsigned RegNo,
110                                             uint64_t Address,
111                                             const void *Decoder);
112
113static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
114                                           unsigned Insn,
115                                           uint64_t Address,
116                                           const void *Decoder);
117
118static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
119                                            unsigned RegNo,
120                                            uint64_t Address,
121                                            const void *Decoder);
122
123static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
124                                             unsigned RegNo,
125                                             uint64_t Address,
126                                             const void *Decoder);
127
128static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
129                                             unsigned RegNo,
130                                             uint64_t Address,
131                                             const void *Decoder);
132
133static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
134                                              unsigned RegNo,
135                                              uint64_t Address,
136                                              const void *Decoder);
137
138static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
139                                           unsigned RegNo,
140                                           uint64_t Address,
141                                           const void *Decoder);
142
143static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
144                                           unsigned RegNo,
145                                           uint64_t Address,
146                                           const void *Decoder);
147
148static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
149                                              unsigned Insn,
150                                              uint64_t Address,
151                                              const void *Decoder);
152
153static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
154                                              unsigned RegNo,
155                                              uint64_t Address,
156                                              const void *Decoder);
157
158static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
159                                                unsigned RegNo,
160                                                uint64_t Address,
161                                                const void *Decoder);
162
163static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
164                                               unsigned RegNo,
165                                               uint64_t Address,
166                                               const void *Decoder);
167
168static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
169                                               unsigned RegNo,
170                                               uint64_t Address,
171                                               const void *Decoder);
172
173static DecodeStatus DecodeBranchTarget(MCInst &Inst,
174                                       unsigned Offset,
175                                       uint64_t Address,
176                                       const void *Decoder);
177
178static DecodeStatus DecodeJumpTarget(MCInst &Inst,
179                                     unsigned Insn,
180                                     uint64_t Address,
181                                     const void *Decoder);
182
183static DecodeStatus DecodeMem(MCInst &Inst,
184                              unsigned Insn,
185                              uint64_t Address,
186                              const void *Decoder);
187
188static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
189                                     unsigned Insn,
190                                     uint64_t Address,
191                                     const void *Decoder);
192
193static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
194                                     unsigned Insn,
195                                     uint64_t Address,
196                                     const void *Decoder);
197
198static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
199                               uint64_t Address,
200                               const void *Decoder);
201
202static DecodeStatus DecodeSimm16(MCInst &Inst,
203                                 unsigned Insn,
204                                 uint64_t Address,
205                                 const void *Decoder);
206
207static DecodeStatus DecodeInsSize(MCInst &Inst,
208                                  unsigned Insn,
209                                  uint64_t Address,
210                                  const void *Decoder);
211
212static DecodeStatus DecodeExtSize(MCInst &Inst,
213                                  unsigned Insn,
214                                  uint64_t Address,
215                                  const void *Decoder);
216
217namespace llvm {
218extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
219              TheMips64elTarget;
220}
221
222static MCDisassembler *createMipsDisassembler(
223                       const Target &T,
224                       const MCSubtargetInfo &STI) {
225  return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
226}
227
228static MCDisassembler *createMipselDisassembler(
229                       const Target &T,
230                       const MCSubtargetInfo &STI) {
231  return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
232}
233
234static MCDisassembler *createMips64Disassembler(
235                       const Target &T,
236                       const MCSubtargetInfo &STI) {
237  return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
238}
239
240static MCDisassembler *createMips64elDisassembler(
241                       const Target &T,
242                       const MCSubtargetInfo &STI) {
243  return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
244}
245
246extern "C" void LLVMInitializeMipsDisassembler() {
247  // Register the disassembler.
248  TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
249                                         createMipsDisassembler);
250  TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
251                                         createMipselDisassembler);
252  TargetRegistry::RegisterMCDisassembler(TheMips64Target,
253                                         createMips64Disassembler);
254  TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
255                                         createMips64elDisassembler);
256}
257
258
259#include "MipsGenDisassemblerTables.inc"
260
261  /// readInstruction - read four bytes from the MemoryObject
262  /// and return 32 bit word sorted according to the given endianess
263static DecodeStatus readInstruction32(const MemoryObject &region,
264                                      uint64_t address,
265                                      uint64_t &size,
266                                      uint32_t &insn,
267                                      bool isBigEndian,
268                                      bool IsMicroMips) {
269  uint8_t Bytes[4];
270
271  // We want to read exactly 4 Bytes of data.
272  if (region.readBytes(address, 4, Bytes) == -1) {
273    size = 0;
274    return MCDisassembler::Fail;
275  }
276
277  if (isBigEndian) {
278    // Encoded as a big-endian 32-bit word in the stream.
279    insn = (Bytes[3] <<  0) |
280           (Bytes[2] <<  8) |
281           (Bytes[1] << 16) |
282           (Bytes[0] << 24);
283  }
284  else {
285    // Encoded as a small-endian 32-bit word in the stream.
286    // Little-endian byte ordering:
287    //   mips32r2:   4 | 3 | 2 | 1
288    //   microMIPS:  2 | 1 | 4 | 3
289    if (IsMicroMips) {
290      insn = (Bytes[2] <<  0) |
291             (Bytes[3] <<  8) |
292             (Bytes[0] << 16) |
293             (Bytes[1] << 24);
294    } else {
295      insn = (Bytes[0] <<  0) |
296             (Bytes[1] <<  8) |
297             (Bytes[2] << 16) |
298             (Bytes[3] << 24);
299    }
300  }
301
302  return MCDisassembler::Success;
303}
304
305DecodeStatus
306MipsDisassembler::getInstruction(MCInst &instr,
307                                 uint64_t &Size,
308                                 const MemoryObject &Region,
309                                 uint64_t Address,
310                                 raw_ostream &vStream,
311                                 raw_ostream &cStream) const {
312  uint32_t Insn;
313
314  DecodeStatus Result = readInstruction32(Region, Address, Size,
315                                          Insn, isBigEndian, IsMicroMips);
316  if (Result == MCDisassembler::Fail)
317    return MCDisassembler::Fail;
318
319  if (IsMicroMips) {
320    // Calling the auto-generated decoder function.
321    Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
322                               this, STI);
323    if (Result != MCDisassembler::Fail) {
324      Size = 4;
325      return Result;
326    }
327    return MCDisassembler::Fail;
328  }
329
330  // Calling the auto-generated decoder function.
331  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
332                             this, STI);
333  if (Result != MCDisassembler::Fail) {
334    Size = 4;
335    return Result;
336  }
337
338  return MCDisassembler::Fail;
339}
340
341DecodeStatus
342Mips64Disassembler::getInstruction(MCInst &instr,
343                                   uint64_t &Size,
344                                   const MemoryObject &Region,
345                                   uint64_t Address,
346                                   raw_ostream &vStream,
347                                   raw_ostream &cStream) const {
348  uint32_t Insn;
349
350  DecodeStatus Result = readInstruction32(Region, Address, Size,
351                                          Insn, isBigEndian, false);
352  if (Result == MCDisassembler::Fail)
353    return MCDisassembler::Fail;
354
355  // Calling the auto-generated decoder function.
356  Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
357                             this, STI);
358  if (Result != MCDisassembler::Fail) {
359    Size = 4;
360    return Result;
361  }
362  // If we fail to decode in Mips64 decoder space we can try in Mips32
363  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
364                             this, STI);
365  if (Result != MCDisassembler::Fail) {
366    Size = 4;
367    return Result;
368  }
369
370  return MCDisassembler::Fail;
371}
372
373static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
374  const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
375  return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
376}
377
378static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
379                                                 unsigned RegNo,
380                                                 uint64_t Address,
381                                                 const void *Decoder) {
382
383  return MCDisassembler::Fail;
384
385}
386
387static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
388                                             unsigned RegNo,
389                                             uint64_t Address,
390                                             const void *Decoder) {
391
392  if (RegNo > 31)
393    return MCDisassembler::Fail;
394
395  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
396  Inst.addOperand(MCOperand::CreateReg(Reg));
397  return MCDisassembler::Success;
398}
399
400static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
401                                             unsigned RegNo,
402                                             uint64_t Address,
403                                             const void *Decoder) {
404  if (RegNo > 31)
405    return MCDisassembler::Fail;
406  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
407  Inst.addOperand(MCOperand::CreateReg(Reg));
408  return MCDisassembler::Success;
409}
410
411static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
412                                           unsigned RegNo,
413                                           uint64_t Address,
414                                           const void *Decoder) {
415  if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
416    return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
417
418  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
419}
420
421static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
422                                            unsigned RegNo,
423                                            uint64_t Address,
424                                            const void *Decoder) {
425  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
426}
427
428static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
429                                             unsigned RegNo,
430                                             uint64_t Address,
431                                             const void *Decoder) {
432  if (RegNo > 31)
433    return MCDisassembler::Fail;
434
435  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
436  Inst.addOperand(MCOperand::CreateReg(Reg));
437  return MCDisassembler::Success;
438}
439
440static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
441                                             unsigned RegNo,
442                                             uint64_t Address,
443                                             const void *Decoder) {
444  if (RegNo > 31)
445    return MCDisassembler::Fail;
446
447  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
448  Inst.addOperand(MCOperand::CreateReg(Reg));
449  return MCDisassembler::Success;
450}
451
452static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
453                                              unsigned RegNo,
454                                              uint64_t Address,
455                                              const void *Decoder) {
456  if (RegNo > 31)
457    return MCDisassembler::Fail;
458
459  unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
460  Inst.addOperand(MCOperand::CreateReg(Reg));
461  return MCDisassembler::Success;
462}
463
464static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
465                                           unsigned RegNo,
466                                           uint64_t Address,
467                                           const void *Decoder) {
468  if (RegNo > 31)
469    return MCDisassembler::Fail;
470  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
471  Inst.addOperand(MCOperand::CreateReg(Reg));
472  return MCDisassembler::Success;
473}
474
475static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
476                                           unsigned RegNo,
477                                           uint64_t Address,
478                                           const void *Decoder) {
479  if (RegNo > 7)
480    return MCDisassembler::Fail;
481  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
482  Inst.addOperand(MCOperand::CreateReg(Reg));
483  return MCDisassembler::Success;
484}
485
486static DecodeStatus DecodeMem(MCInst &Inst,
487                              unsigned Insn,
488                              uint64_t Address,
489                              const void *Decoder) {
490  int Offset = SignExtend32<16>(Insn & 0xffff);
491  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
492  unsigned Base = fieldFromInstruction(Insn, 21, 5);
493
494  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
495  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
496
497  if(Inst.getOpcode() == Mips::SC){
498    Inst.addOperand(MCOperand::CreateReg(Reg));
499  }
500
501  Inst.addOperand(MCOperand::CreateReg(Reg));
502  Inst.addOperand(MCOperand::CreateReg(Base));
503  Inst.addOperand(MCOperand::CreateImm(Offset));
504
505  return MCDisassembler::Success;
506}
507
508static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
509                                     unsigned Insn,
510                                     uint64_t Address,
511                                     const void *Decoder) {
512  int Offset = SignExtend32<12>(Insn & 0x0fff);
513  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
514  unsigned Base = fieldFromInstruction(Insn, 16, 5);
515
516  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
517  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
518
519  Inst.addOperand(MCOperand::CreateReg(Reg));
520  Inst.addOperand(MCOperand::CreateReg(Base));
521  Inst.addOperand(MCOperand::CreateImm(Offset));
522
523  return MCDisassembler::Success;
524}
525
526static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
527                                     unsigned Insn,
528                                     uint64_t Address,
529                                     const void *Decoder) {
530  int Offset = SignExtend32<16>(Insn & 0xffff);
531  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
532  unsigned Base = fieldFromInstruction(Insn, 16, 5);
533
534  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
535  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
536
537  Inst.addOperand(MCOperand::CreateReg(Reg));
538  Inst.addOperand(MCOperand::CreateReg(Base));
539  Inst.addOperand(MCOperand::CreateImm(Offset));
540
541  return MCDisassembler::Success;
542}
543
544static DecodeStatus DecodeFMem(MCInst &Inst,
545                               unsigned Insn,
546                               uint64_t Address,
547                               const void *Decoder) {
548  int Offset = SignExtend32<16>(Insn & 0xffff);
549  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
550  unsigned Base = fieldFromInstruction(Insn, 21, 5);
551
552  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
553  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
554
555  Inst.addOperand(MCOperand::CreateReg(Reg));
556  Inst.addOperand(MCOperand::CreateReg(Base));
557  Inst.addOperand(MCOperand::CreateImm(Offset));
558
559  return MCDisassembler::Success;
560}
561
562
563static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
564                                              unsigned RegNo,
565                                              uint64_t Address,
566                                              const void *Decoder) {
567  // Currently only hardware register 29 is supported.
568  if (RegNo != 29)
569    return  MCDisassembler::Fail;
570  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
571  return MCDisassembler::Success;
572}
573
574static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
575                                              unsigned RegNo,
576                                              uint64_t Address,
577                                              const void *Decoder) {
578  if (RegNo > 30 || RegNo %2)
579    return MCDisassembler::Fail;
580
581  ;
582  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
583  Inst.addOperand(MCOperand::CreateReg(Reg));
584  return MCDisassembler::Success;
585}
586
587static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
588                                                unsigned RegNo,
589                                                uint64_t Address,
590                                                const void *Decoder) {
591  if (RegNo >= 4)
592    return MCDisassembler::Fail;
593
594  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
595  Inst.addOperand(MCOperand::CreateReg(Reg));
596  return MCDisassembler::Success;
597}
598
599static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
600                                               unsigned RegNo,
601                                               uint64_t Address,
602                                               const void *Decoder) {
603  if (RegNo >= 4)
604    return MCDisassembler::Fail;
605
606  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
607  Inst.addOperand(MCOperand::CreateReg(Reg));
608  return MCDisassembler::Success;
609}
610
611static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
612                                               unsigned RegNo,
613                                               uint64_t Address,
614                                               const void *Decoder) {
615  if (RegNo >= 4)
616    return MCDisassembler::Fail;
617
618  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
619  Inst.addOperand(MCOperand::CreateReg(Reg));
620  return MCDisassembler::Success;
621}
622
623static DecodeStatus DecodeBranchTarget(MCInst &Inst,
624                                       unsigned Offset,
625                                       uint64_t Address,
626                                       const void *Decoder) {
627  unsigned BranchOffset = Offset & 0xffff;
628  BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
629  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
630  return MCDisassembler::Success;
631}
632
633static DecodeStatus DecodeJumpTarget(MCInst &Inst,
634                                     unsigned Insn,
635                                     uint64_t Address,
636                                     const void *Decoder) {
637
638  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
639  Inst.addOperand(MCOperand::CreateImm(JumpOffset));
640  return MCDisassembler::Success;
641}
642
643
644static DecodeStatus DecodeSimm16(MCInst &Inst,
645                                 unsigned Insn,
646                                 uint64_t Address,
647                                 const void *Decoder) {
648  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
649  return MCDisassembler::Success;
650}
651
652static DecodeStatus DecodeInsSize(MCInst &Inst,
653                                  unsigned Insn,
654                                  uint64_t Address,
655                                  const void *Decoder) {
656  // First we need to grab the pos(lsb) from MCInst.
657  int Pos = Inst.getOperand(2).getImm();
658  int Size = (int) Insn - Pos + 1;
659  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
660  return MCDisassembler::Success;
661}
662
663static DecodeStatus DecodeExtSize(MCInst &Inst,
664                                  unsigned Insn,
665                                  uint64_t Address,
666                                  const void *Decoder) {
667  int Size = (int) Insn  + 1;
668  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
669  return MCDisassembler::Success;
670}
671