MipsDisassembler.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the Mips Disassembler.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Mips.h"
15#include "MipsRegisterInfo.h"
16#include "MipsSubtarget.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCDisassembler.h"
19#include "llvm/MC/MCFixedLenDisassembler.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/Support/MathExtras.h"
23#include "llvm/Support/MemoryObject.h"
24#include "llvm/Support/TargetRegistry.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "mips-disassembler"
29
30typedef MCDisassembler::DecodeStatus DecodeStatus;
31
32namespace {
33
34/// MipsDisassemblerBase - a disasembler class for Mips.
35class MipsDisassemblerBase : public MCDisassembler {
36public:
37  /// Constructor     - Initializes the disassembler.
38  ///
39  MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
40                       bool bigEndian) :
41    MCDisassembler(STI, Ctx),
42    IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
43
44  virtual ~MipsDisassemblerBase() {}
45
46  bool isN64() const { return IsN64; }
47
48private:
49  bool IsN64;
50protected:
51  bool isBigEndian;
52};
53
54/// MipsDisassembler - a disasembler class for Mips32.
55class MipsDisassembler : public MipsDisassemblerBase {
56  bool IsMicroMips;
57public:
58  /// Constructor     - Initializes the disassembler.
59  ///
60  MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
61                   bool bigEndian) :
62    MipsDisassemblerBase(STI, Ctx, bigEndian) {
63      IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
64    }
65
66  bool isMips32r6() const {
67    return STI.getFeatureBits() & Mips::FeatureMips32r6;
68  }
69
70  /// getInstruction - See MCDisassembler.
71  DecodeStatus getInstruction(MCInst &instr,
72                              uint64_t &size,
73                              const MemoryObject &region,
74                              uint64_t address,
75                              raw_ostream &vStream,
76                              raw_ostream &cStream) const override;
77};
78
79
80/// Mips64Disassembler - a disasembler class for Mips64.
81class Mips64Disassembler : public MipsDisassemblerBase {
82public:
83  /// Constructor     - Initializes the disassembler.
84  ///
85  Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
86                     bool bigEndian) :
87    MipsDisassemblerBase(STI, Ctx, bigEndian) {}
88
89  /// getInstruction - See MCDisassembler.
90  DecodeStatus getInstruction(MCInst &instr,
91                              uint64_t &size,
92                              const MemoryObject &region,
93                              uint64_t address,
94                              raw_ostream &vStream,
95                              raw_ostream &cStream) const override;
96};
97
98} // end anonymous namespace
99
100// Forward declare these because the autogenerated code will reference them.
101// Definitions are further down.
102static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
103                                             unsigned RegNo,
104                                             uint64_t Address,
105                                             const void *Decoder);
106
107static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
108                                                 unsigned RegNo,
109                                                 uint64_t Address,
110                                                 const void *Decoder);
111
112static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
113                                             unsigned RegNo,
114                                             uint64_t Address,
115                                             const void *Decoder);
116
117static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
118                                           unsigned Insn,
119                                           uint64_t Address,
120                                           const void *Decoder);
121
122static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
123                                            unsigned RegNo,
124                                            uint64_t Address,
125                                            const void *Decoder);
126
127static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
128                                             unsigned RegNo,
129                                             uint64_t Address,
130                                             const void *Decoder);
131
132static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
133                                             unsigned RegNo,
134                                             uint64_t Address,
135                                             const void *Decoder);
136
137static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
138                                              unsigned RegNo,
139                                              uint64_t Address,
140                                              const void *Decoder);
141
142static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
143                                           unsigned RegNo,
144                                           uint64_t Address,
145                                           const void *Decoder);
146
147static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
148                                           unsigned RegNo,
149                                           uint64_t Address,
150                                           const void *Decoder);
151
152static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
153                                              unsigned Insn,
154                                              uint64_t Address,
155                                              const void *Decoder);
156
157static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
158                                              unsigned RegNo,
159                                              uint64_t Address,
160                                              const void *Decoder);
161
162static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
163                                                unsigned RegNo,
164                                                uint64_t Address,
165                                                const void *Decoder);
166
167static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
168                                               unsigned RegNo,
169                                               uint64_t Address,
170                                               const void *Decoder);
171
172static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
173                                               unsigned RegNo,
174                                               uint64_t Address,
175                                               const void *Decoder);
176
177static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
178                                               unsigned RegNo,
179                                               uint64_t Address,
180                                               const void *Decoder);
181
182static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
183                                               unsigned RegNo,
184                                               uint64_t Address,
185                                               const void *Decoder);
186
187static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
188                                               unsigned RegNo,
189                                               uint64_t Address,
190                                               const void *Decoder);
191
192static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
193                                               unsigned RegNo,
194                                               uint64_t Address,
195                                               const void *Decoder);
196
197static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
198                                               unsigned RegNo,
199                                               uint64_t Address,
200                                               const void *Decoder);
201
202static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
203                                            unsigned RegNo,
204                                            uint64_t Address,
205                                            const void *Decoder);
206
207static DecodeStatus DecodeBranchTarget(MCInst &Inst,
208                                       unsigned Offset,
209                                       uint64_t Address,
210                                       const void *Decoder);
211
212static DecodeStatus DecodeJumpTarget(MCInst &Inst,
213                                     unsigned Insn,
214                                     uint64_t Address,
215                                     const void *Decoder);
216
217static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
218                                         unsigned Offset,
219                                         uint64_t Address,
220                                         const void *Decoder);
221
222static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
223                                         unsigned Offset,
224                                         uint64_t Address,
225                                         const void *Decoder);
226
227// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
228// shifted left by 1 bit.
229static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
230                                         unsigned Offset,
231                                         uint64_t Address,
232                                         const void *Decoder);
233
234// DecodeJumpTargetMM - Decode microMIPS jump target, which is
235// shifted left by 1 bit.
236static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
237                                       unsigned Insn,
238                                       uint64_t Address,
239                                       const void *Decoder);
240
241static DecodeStatus DecodeMem(MCInst &Inst,
242                              unsigned Insn,
243                              uint64_t Address,
244                              const void *Decoder);
245
246static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
247                                    uint64_t Address, const void *Decoder);
248
249static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
250                                     unsigned Insn,
251                                     uint64_t Address,
252                                     const void *Decoder);
253
254static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
255                                     unsigned Insn,
256                                     uint64_t Address,
257                                     const void *Decoder);
258
259static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
260                               uint64_t Address,
261                               const void *Decoder);
262
263static DecodeStatus DecodeSimm16(MCInst &Inst,
264                                 unsigned Insn,
265                                 uint64_t Address,
266                                 const void *Decoder);
267
268// Decode the immediate field of an LSA instruction which
269// is off by one.
270static DecodeStatus DecodeLSAImm(MCInst &Inst,
271                                 unsigned Insn,
272                                 uint64_t Address,
273                                 const void *Decoder);
274
275static DecodeStatus DecodeInsSize(MCInst &Inst,
276                                  unsigned Insn,
277                                  uint64_t Address,
278                                  const void *Decoder);
279
280static DecodeStatus DecodeExtSize(MCInst &Inst,
281                                  unsigned Insn,
282                                  uint64_t Address,
283                                  const void *Decoder);
284
285static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
286                                     uint64_t Address, const void *Decoder);
287
288/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
289/// handle.
290template <typename InsnType>
291static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
292                                   const void *Decoder);
293
294template <typename InsnType>
295static DecodeStatus
296DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
297                      const void *Decoder);
298
299template <typename InsnType>
300static DecodeStatus
301DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
302                       const void *Decoder);
303
304template <typename InsnType>
305static DecodeStatus
306DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
307                       const void *Decoder);
308
309template <typename InsnType>
310static DecodeStatus
311DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
312                       const void *Decoder);
313
314template <typename InsnType>
315static DecodeStatus
316DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
317                      const void *Decoder);
318
319namespace llvm {
320extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
321              TheMips64elTarget;
322}
323
324static MCDisassembler *createMipsDisassembler(
325                       const Target &T,
326                       const MCSubtargetInfo &STI,
327                       MCContext &Ctx) {
328  return new MipsDisassembler(STI, Ctx, true);
329}
330
331static MCDisassembler *createMipselDisassembler(
332                       const Target &T,
333                       const MCSubtargetInfo &STI,
334                       MCContext &Ctx) {
335  return new MipsDisassembler(STI, Ctx, false);
336}
337
338static MCDisassembler *createMips64Disassembler(
339                       const Target &T,
340                       const MCSubtargetInfo &STI,
341                       MCContext &Ctx) {
342  return new Mips64Disassembler(STI, Ctx, true);
343}
344
345static MCDisassembler *createMips64elDisassembler(
346                       const Target &T,
347                       const MCSubtargetInfo &STI,
348                       MCContext &Ctx) {
349  return new Mips64Disassembler(STI, Ctx, false);
350}
351
352extern "C" void LLVMInitializeMipsDisassembler() {
353  // Register the disassembler.
354  TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
355                                         createMipsDisassembler);
356  TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
357                                         createMipselDisassembler);
358  TargetRegistry::RegisterMCDisassembler(TheMips64Target,
359                                         createMips64Disassembler);
360  TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
361                                         createMips64elDisassembler);
362}
363
364#include "MipsGenDisassemblerTables.inc"
365
366static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
367  const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
368  const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
369  return *(RegInfo->getRegClass(RC).begin() + RegNo);
370}
371
372template <typename InsnType>
373static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
374                                   const void *Decoder) {
375  typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
376  // The size of the n field depends on the element size
377  // The register class also depends on this.
378  InsnType tmp = fieldFromInstruction(insn, 17, 5);
379  unsigned NSize = 0;
380  DecodeFN RegDecoder = nullptr;
381  if ((tmp & 0x18) == 0x00) { // INSVE_B
382    NSize = 4;
383    RegDecoder = DecodeMSA128BRegisterClass;
384  } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
385    NSize = 3;
386    RegDecoder = DecodeMSA128HRegisterClass;
387  } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
388    NSize = 2;
389    RegDecoder = DecodeMSA128WRegisterClass;
390  } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
391    NSize = 1;
392    RegDecoder = DecodeMSA128DRegisterClass;
393  } else
394    llvm_unreachable("Invalid encoding");
395
396  assert(NSize != 0 && RegDecoder != nullptr);
397
398  // $wd
399  tmp = fieldFromInstruction(insn, 6, 5);
400  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
401    return MCDisassembler::Fail;
402  // $wd_in
403  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
404    return MCDisassembler::Fail;
405  // $n
406  tmp = fieldFromInstruction(insn, 16, NSize);
407  MI.addOperand(MCOperand::CreateImm(tmp));
408  // $ws
409  tmp = fieldFromInstruction(insn, 11, 5);
410  if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
411    return MCDisassembler::Fail;
412  // $n2
413  MI.addOperand(MCOperand::CreateImm(0));
414
415  return MCDisassembler::Success;
416}
417
418template <typename InsnType>
419static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
420                                          uint64_t Address,
421                                          const void *Decoder) {
422  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
423  // (otherwise we would have matched the ADDI instruction from the earlier
424  // ISA's instead).
425  //
426  // We have:
427  //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
428  //      BOVC if rs >= rt
429  //      BEQZALC if rs == 0 && rt != 0
430  //      BEQC if rs < rt && rs != 0
431
432  InsnType Rs = fieldFromInstruction(insn, 21, 5);
433  InsnType Rt = fieldFromInstruction(insn, 16, 5);
434  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
435  bool HasRs = false;
436
437  if (Rs >= Rt) {
438    MI.setOpcode(Mips::BOVC);
439    HasRs = true;
440  } else if (Rs != 0 && Rs < Rt) {
441    MI.setOpcode(Mips::BEQC);
442    HasRs = true;
443  } else
444    MI.setOpcode(Mips::BEQZALC);
445
446  if (HasRs)
447    MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
448                                       Rs)));
449
450  MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
451                                     Rt)));
452  MI.addOperand(MCOperand::CreateImm(Imm));
453
454  return MCDisassembler::Success;
455}
456
457template <typename InsnType>
458static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
459                                           uint64_t Address,
460                                           const void *Decoder) {
461  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
462  // (otherwise we would have matched the ADDI instruction from the earlier
463  // ISA's instead).
464  //
465  // We have:
466  //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
467  //      BNVC if rs >= rt
468  //      BNEZALC if rs == 0 && rt != 0
469  //      BNEC if rs < rt && rs != 0
470
471  InsnType Rs = fieldFromInstruction(insn, 21, 5);
472  InsnType Rt = fieldFromInstruction(insn, 16, 5);
473  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
474  bool HasRs = false;
475
476  if (Rs >= Rt) {
477    MI.setOpcode(Mips::BNVC);
478    HasRs = true;
479  } else if (Rs != 0 && Rs < Rt) {
480    MI.setOpcode(Mips::BNEC);
481    HasRs = true;
482  } else
483    MI.setOpcode(Mips::BNEZALC);
484
485  if (HasRs)
486    MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
487                                       Rs)));
488
489  MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
490                                     Rt)));
491  MI.addOperand(MCOperand::CreateImm(Imm));
492
493  return MCDisassembler::Success;
494}
495
496template <typename InsnType>
497static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
498                                           uint64_t Address,
499                                           const void *Decoder) {
500  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
501  // (otherwise we would have matched the BLEZL instruction from the earlier
502  // ISA's instead).
503  //
504  // We have:
505  //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
506  //      Invalid if rs == 0
507  //      BLEZC   if rs == 0  && rt != 0
508  //      BGEZC   if rs == rt && rt != 0
509  //      BGEC    if rs != rt && rs != 0  && rt != 0
510
511  InsnType Rs = fieldFromInstruction(insn, 21, 5);
512  InsnType Rt = fieldFromInstruction(insn, 16, 5);
513  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
514
515  if (Rt == 0)
516    return MCDisassembler::Fail;
517  else if (Rs == 0)
518    MI.setOpcode(Mips::BLEZC);
519  else if (Rs == Rt)
520    MI.setOpcode(Mips::BGEZC);
521  else
522    return MCDisassembler::Fail; // FIXME: BGEC is not implemented yet.
523
524  MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
525                                     Rt)));
526
527  MI.addOperand(MCOperand::CreateImm(Imm));
528
529  return MCDisassembler::Success;
530}
531
532template <typename InsnType>
533static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
534                                           uint64_t Address,
535                                           const void *Decoder) {
536  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
537  // (otherwise we would have matched the BGTZL instruction from the earlier
538  // ISA's instead).
539  //
540  // We have:
541  //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
542  //      Invalid if rs == 0
543  //      BGTZC   if rs == 0  && rt != 0
544  //      BLTZC   if rs == rt && rt != 0
545  //      BLTC    if rs != rt && rs != 0  && rt != 0
546
547  InsnType Rs = fieldFromInstruction(insn, 21, 5);
548  InsnType Rt = fieldFromInstruction(insn, 16, 5);
549  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
550
551  if (Rt == 0)
552    return MCDisassembler::Fail;
553  else if (Rs == 0)
554    MI.setOpcode(Mips::BGTZC);
555  else if (Rs == Rt)
556    MI.setOpcode(Mips::BLTZC);
557  else
558    return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
559
560  MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
561                                     Rt)));
562
563  MI.addOperand(MCOperand::CreateImm(Imm));
564
565  return MCDisassembler::Success;
566}
567
568template <typename InsnType>
569static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
570                                          uint64_t Address,
571                                          const void *Decoder) {
572  // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
573  // (otherwise we would have matched the BGTZ instruction from the earlier
574  // ISA's instead).
575  //
576  // We have:
577  //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
578  //      BGTZ    if rt == 0
579  //      BGTZALC if rs == 0 && rt != 0
580  //      BLTZALC if rs != 0 && rs == rt
581  //      BLTUC   if rs != 0 && rs != rt
582
583  InsnType Rs = fieldFromInstruction(insn, 21, 5);
584  InsnType Rt = fieldFromInstruction(insn, 16, 5);
585  InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
586  bool HasRs = false;
587  bool HasRt = false;
588
589  if (Rt == 0) {
590    MI.setOpcode(Mips::BGTZ);
591    HasRs = true;
592  } else if (Rs == 0) {
593    MI.setOpcode(Mips::BGTZALC);
594    HasRt = true;
595  } else if (Rs == Rt) {
596    MI.setOpcode(Mips::BLTZALC);
597    HasRs = true;
598  } else
599    return MCDisassembler::Fail; // BLTUC not implemented yet
600
601  if (HasRs)
602    MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
603                                       Rs)));
604
605  if (HasRt)
606    MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
607                                       Rt)));
608
609  MI.addOperand(MCOperand::CreateImm(Imm));
610
611  return MCDisassembler::Success;
612}
613
614  /// readInstruction - read four bytes from the MemoryObject
615  /// and return 32 bit word sorted according to the given endianess
616static DecodeStatus readInstruction32(const MemoryObject &region,
617                                      uint64_t address,
618                                      uint64_t &size,
619                                      uint32_t &insn,
620                                      bool isBigEndian,
621                                      bool IsMicroMips) {
622  uint8_t Bytes[4];
623
624  // We want to read exactly 4 Bytes of data.
625  if (region.readBytes(address, 4, Bytes) == -1) {
626    size = 0;
627    return MCDisassembler::Fail;
628  }
629
630  if (isBigEndian) {
631    // Encoded as a big-endian 32-bit word in the stream.
632    insn = (Bytes[3] <<  0) |
633           (Bytes[2] <<  8) |
634           (Bytes[1] << 16) |
635           (Bytes[0] << 24);
636  }
637  else {
638    // Encoded as a small-endian 32-bit word in the stream.
639    // Little-endian byte ordering:
640    //   mips32r2:   4 | 3 | 2 | 1
641    //   microMIPS:  2 | 1 | 4 | 3
642    if (IsMicroMips) {
643      insn = (Bytes[2] <<  0) |
644             (Bytes[3] <<  8) |
645             (Bytes[0] << 16) |
646             (Bytes[1] << 24);
647    } else {
648      insn = (Bytes[0] <<  0) |
649             (Bytes[1] <<  8) |
650             (Bytes[2] << 16) |
651             (Bytes[3] << 24);
652    }
653  }
654
655  return MCDisassembler::Success;
656}
657
658DecodeStatus
659MipsDisassembler::getInstruction(MCInst &instr,
660                                 uint64_t &Size,
661                                 const MemoryObject &Region,
662                                 uint64_t Address,
663                                 raw_ostream &vStream,
664                                 raw_ostream &cStream) const {
665  uint32_t Insn;
666
667  DecodeStatus Result = readInstruction32(Region, Address, Size,
668                                          Insn, isBigEndian, IsMicroMips);
669  if (Result == MCDisassembler::Fail)
670    return MCDisassembler::Fail;
671
672  if (IsMicroMips) {
673    // Calling the auto-generated decoder function.
674    Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
675                               this, STI);
676    if (Result != MCDisassembler::Fail) {
677      Size = 4;
678      return Result;
679    }
680    return MCDisassembler::Fail;
681  }
682
683  if (isMips32r6()) {
684    Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
685                               Address, this, STI);
686    if (Result != MCDisassembler::Fail) {
687      Size = 4;
688      return Result;
689    }
690  }
691
692  // Calling the auto-generated decoder function.
693  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
694                             this, STI);
695  if (Result != MCDisassembler::Fail) {
696    Size = 4;
697    return Result;
698  }
699
700  return MCDisassembler::Fail;
701}
702
703DecodeStatus
704Mips64Disassembler::getInstruction(MCInst &instr,
705                                   uint64_t &Size,
706                                   const MemoryObject &Region,
707                                   uint64_t Address,
708                                   raw_ostream &vStream,
709                                   raw_ostream &cStream) const {
710  uint32_t Insn;
711
712  DecodeStatus Result = readInstruction32(Region, Address, Size,
713                                          Insn, isBigEndian, false);
714  if (Result == MCDisassembler::Fail)
715    return MCDisassembler::Fail;
716
717  // Calling the auto-generated decoder function.
718  Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
719                             this, STI);
720  if (Result != MCDisassembler::Fail) {
721    Size = 4;
722    return Result;
723  }
724  // If we fail to decode in Mips64 decoder space we can try in Mips32
725  Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
726                             this, STI);
727  if (Result != MCDisassembler::Fail) {
728    Size = 4;
729    return Result;
730  }
731
732  return MCDisassembler::Fail;
733}
734
735static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
736                                                 unsigned RegNo,
737                                                 uint64_t Address,
738                                                 const void *Decoder) {
739
740  return MCDisassembler::Fail;
741
742}
743
744static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
745                                             unsigned RegNo,
746                                             uint64_t Address,
747                                             const void *Decoder) {
748
749  if (RegNo > 31)
750    return MCDisassembler::Fail;
751
752  unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
753  Inst.addOperand(MCOperand::CreateReg(Reg));
754  return MCDisassembler::Success;
755}
756
757static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
758                                             unsigned RegNo,
759                                             uint64_t Address,
760                                             const void *Decoder) {
761  if (RegNo > 31)
762    return MCDisassembler::Fail;
763  unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
764  Inst.addOperand(MCOperand::CreateReg(Reg));
765  return MCDisassembler::Success;
766}
767
768static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
769                                           unsigned RegNo,
770                                           uint64_t Address,
771                                           const void *Decoder) {
772  if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
773    return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
774
775  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
776}
777
778static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
779                                            unsigned RegNo,
780                                            uint64_t Address,
781                                            const void *Decoder) {
782  return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
783}
784
785static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
786                                             unsigned RegNo,
787                                             uint64_t Address,
788                                             const void *Decoder) {
789  if (RegNo > 31)
790    return MCDisassembler::Fail;
791
792  unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
793  Inst.addOperand(MCOperand::CreateReg(Reg));
794  return MCDisassembler::Success;
795}
796
797static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
798                                             unsigned RegNo,
799                                             uint64_t Address,
800                                             const void *Decoder) {
801  if (RegNo > 31)
802    return MCDisassembler::Fail;
803
804  unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
805  Inst.addOperand(MCOperand::CreateReg(Reg));
806  return MCDisassembler::Success;
807}
808
809static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
810                                              unsigned RegNo,
811                                              uint64_t Address,
812                                              const void *Decoder) {
813  if (RegNo > 31)
814    return MCDisassembler::Fail;
815
816  unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
817  Inst.addOperand(MCOperand::CreateReg(Reg));
818  return MCDisassembler::Success;
819}
820
821static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
822                                           unsigned RegNo,
823                                           uint64_t Address,
824                                           const void *Decoder) {
825  if (RegNo > 31)
826    return MCDisassembler::Fail;
827  unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
828  Inst.addOperand(MCOperand::CreateReg(Reg));
829  return MCDisassembler::Success;
830}
831
832static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
833                                           unsigned RegNo,
834                                           uint64_t Address,
835                                           const void *Decoder) {
836  if (RegNo > 7)
837    return MCDisassembler::Fail;
838  unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
839  Inst.addOperand(MCOperand::CreateReg(Reg));
840  return MCDisassembler::Success;
841}
842
843static DecodeStatus DecodeMem(MCInst &Inst,
844                              unsigned Insn,
845                              uint64_t Address,
846                              const void *Decoder) {
847  int Offset = SignExtend32<16>(Insn & 0xffff);
848  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
849  unsigned Base = fieldFromInstruction(Insn, 21, 5);
850
851  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
852  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
853
854  if(Inst.getOpcode() == Mips::SC){
855    Inst.addOperand(MCOperand::CreateReg(Reg));
856  }
857
858  Inst.addOperand(MCOperand::CreateReg(Reg));
859  Inst.addOperand(MCOperand::CreateReg(Base));
860  Inst.addOperand(MCOperand::CreateImm(Offset));
861
862  return MCDisassembler::Success;
863}
864
865static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
866                                    uint64_t Address, const void *Decoder) {
867  int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
868  unsigned Reg = fieldFromInstruction(Insn, 6, 5);
869  unsigned Base = fieldFromInstruction(Insn, 11, 5);
870
871  Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
872  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
873
874  Inst.addOperand(MCOperand::CreateReg(Reg));
875  Inst.addOperand(MCOperand::CreateReg(Base));
876
877  // The immediate field of an LD/ST instruction is scaled which means it must
878  // be multiplied (when decoding) by the size (in bytes) of the instructions'
879  // data format.
880  // .b - 1 byte
881  // .h - 2 bytes
882  // .w - 4 bytes
883  // .d - 8 bytes
884  switch(Inst.getOpcode())
885  {
886  default:
887    assert (0 && "Unexpected instruction");
888    return MCDisassembler::Fail;
889    break;
890  case Mips::LD_B:
891  case Mips::ST_B:
892    Inst.addOperand(MCOperand::CreateImm(Offset));
893    break;
894  case Mips::LD_H:
895  case Mips::ST_H:
896    Inst.addOperand(MCOperand::CreateImm(Offset << 1));
897    break;
898  case Mips::LD_W:
899  case Mips::ST_W:
900    Inst.addOperand(MCOperand::CreateImm(Offset << 2));
901    break;
902  case Mips::LD_D:
903  case Mips::ST_D:
904    Inst.addOperand(MCOperand::CreateImm(Offset << 3));
905    break;
906  }
907
908  return MCDisassembler::Success;
909}
910
911static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
912                                     unsigned Insn,
913                                     uint64_t Address,
914                                     const void *Decoder) {
915  int Offset = SignExtend32<12>(Insn & 0x0fff);
916  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
917  unsigned Base = fieldFromInstruction(Insn, 16, 5);
918
919  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
920  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
921
922  if (Inst.getOpcode() == Mips::SC_MM)
923    Inst.addOperand(MCOperand::CreateReg(Reg));
924
925  Inst.addOperand(MCOperand::CreateReg(Reg));
926  Inst.addOperand(MCOperand::CreateReg(Base));
927  Inst.addOperand(MCOperand::CreateImm(Offset));
928
929  return MCDisassembler::Success;
930}
931
932static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
933                                     unsigned Insn,
934                                     uint64_t Address,
935                                     const void *Decoder) {
936  int Offset = SignExtend32<16>(Insn & 0xffff);
937  unsigned Reg = fieldFromInstruction(Insn, 21, 5);
938  unsigned Base = fieldFromInstruction(Insn, 16, 5);
939
940  Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
941  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
942
943  Inst.addOperand(MCOperand::CreateReg(Reg));
944  Inst.addOperand(MCOperand::CreateReg(Base));
945  Inst.addOperand(MCOperand::CreateImm(Offset));
946
947  return MCDisassembler::Success;
948}
949
950static DecodeStatus DecodeFMem(MCInst &Inst,
951                               unsigned Insn,
952                               uint64_t Address,
953                               const void *Decoder) {
954  int Offset = SignExtend32<16>(Insn & 0xffff);
955  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
956  unsigned Base = fieldFromInstruction(Insn, 21, 5);
957
958  Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
959  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
960
961  Inst.addOperand(MCOperand::CreateReg(Reg));
962  Inst.addOperand(MCOperand::CreateReg(Base));
963  Inst.addOperand(MCOperand::CreateImm(Offset));
964
965  return MCDisassembler::Success;
966}
967
968
969static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
970                                              unsigned RegNo,
971                                              uint64_t Address,
972                                              const void *Decoder) {
973  // Currently only hardware register 29 is supported.
974  if (RegNo != 29)
975    return  MCDisassembler::Fail;
976  Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
977  return MCDisassembler::Success;
978}
979
980static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
981                                              unsigned RegNo,
982                                              uint64_t Address,
983                                              const void *Decoder) {
984  if (RegNo > 30 || RegNo %2)
985    return MCDisassembler::Fail;
986
987  ;
988  unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
989  Inst.addOperand(MCOperand::CreateReg(Reg));
990  return MCDisassembler::Success;
991}
992
993static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
994                                                unsigned RegNo,
995                                                uint64_t Address,
996                                                const void *Decoder) {
997  if (RegNo >= 4)
998    return MCDisassembler::Fail;
999
1000  unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1001  Inst.addOperand(MCOperand::CreateReg(Reg));
1002  return MCDisassembler::Success;
1003}
1004
1005static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1006                                               unsigned RegNo,
1007                                               uint64_t Address,
1008                                               const void *Decoder) {
1009  if (RegNo >= 4)
1010    return MCDisassembler::Fail;
1011
1012  unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1013  Inst.addOperand(MCOperand::CreateReg(Reg));
1014  return MCDisassembler::Success;
1015}
1016
1017static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1018                                               unsigned RegNo,
1019                                               uint64_t Address,
1020                                               const void *Decoder) {
1021  if (RegNo >= 4)
1022    return MCDisassembler::Fail;
1023
1024  unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1025  Inst.addOperand(MCOperand::CreateReg(Reg));
1026  return MCDisassembler::Success;
1027}
1028
1029static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1030                                               unsigned RegNo,
1031                                               uint64_t Address,
1032                                               const void *Decoder) {
1033  if (RegNo > 31)
1034    return MCDisassembler::Fail;
1035
1036  unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1037  Inst.addOperand(MCOperand::CreateReg(Reg));
1038  return MCDisassembler::Success;
1039}
1040
1041static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1042                                               unsigned RegNo,
1043                                               uint64_t Address,
1044                                               const void *Decoder) {
1045  if (RegNo > 31)
1046    return MCDisassembler::Fail;
1047
1048  unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1049  Inst.addOperand(MCOperand::CreateReg(Reg));
1050  return MCDisassembler::Success;
1051}
1052
1053static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1054                                               unsigned RegNo,
1055                                               uint64_t Address,
1056                                               const void *Decoder) {
1057  if (RegNo > 31)
1058    return MCDisassembler::Fail;
1059
1060  unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1061  Inst.addOperand(MCOperand::CreateReg(Reg));
1062  return MCDisassembler::Success;
1063}
1064
1065static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1066                                               unsigned RegNo,
1067                                               uint64_t Address,
1068                                               const void *Decoder) {
1069  if (RegNo > 31)
1070    return MCDisassembler::Fail;
1071
1072  unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1073  Inst.addOperand(MCOperand::CreateReg(Reg));
1074  return MCDisassembler::Success;
1075}
1076
1077static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1078                                               unsigned RegNo,
1079                                               uint64_t Address,
1080                                               const void *Decoder) {
1081  if (RegNo > 7)
1082    return MCDisassembler::Fail;
1083
1084  unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1085  Inst.addOperand(MCOperand::CreateReg(Reg));
1086  return MCDisassembler::Success;
1087}
1088
1089static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1090                                            unsigned RegNo,
1091                                            uint64_t Address,
1092                                            const void *Decoder) {
1093  if (RegNo > 31)
1094    return MCDisassembler::Fail;
1095
1096  unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1097  Inst.addOperand(MCOperand::CreateReg(Reg));
1098  return MCDisassembler::Success;
1099}
1100
1101static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1102                                       unsigned Offset,
1103                                       uint64_t Address,
1104                                       const void *Decoder) {
1105  int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1106  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1107  return MCDisassembler::Success;
1108}
1109
1110static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1111                                     unsigned Insn,
1112                                     uint64_t Address,
1113                                     const void *Decoder) {
1114
1115  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1116  Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1117  return MCDisassembler::Success;
1118}
1119
1120static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1121                                         unsigned Offset,
1122                                         uint64_t Address,
1123                                         const void *Decoder) {
1124  int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1125
1126  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1127  return MCDisassembler::Success;
1128}
1129
1130static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1131                                         unsigned Offset,
1132                                         uint64_t Address,
1133                                         const void *Decoder) {
1134  int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1135
1136  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1137  return MCDisassembler::Success;
1138}
1139
1140static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1141                                         unsigned Offset,
1142                                         uint64_t Address,
1143                                         const void *Decoder) {
1144  int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1145  Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1146  return MCDisassembler::Success;
1147}
1148
1149static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1150                                       unsigned Insn,
1151                                       uint64_t Address,
1152                                       const void *Decoder) {
1153  unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1154  Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1155  return MCDisassembler::Success;
1156}
1157
1158static DecodeStatus DecodeSimm16(MCInst &Inst,
1159                                 unsigned Insn,
1160                                 uint64_t Address,
1161                                 const void *Decoder) {
1162  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1163  return MCDisassembler::Success;
1164}
1165
1166static DecodeStatus DecodeLSAImm(MCInst &Inst,
1167                                 unsigned Insn,
1168                                 uint64_t Address,
1169                                 const void *Decoder) {
1170  // We add one to the immediate field as it was encoded as 'imm - 1'.
1171  Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1172  return MCDisassembler::Success;
1173}
1174
1175static DecodeStatus DecodeInsSize(MCInst &Inst,
1176                                  unsigned Insn,
1177                                  uint64_t Address,
1178                                  const void *Decoder) {
1179  // First we need to grab the pos(lsb) from MCInst.
1180  int Pos = Inst.getOperand(2).getImm();
1181  int Size = (int) Insn - Pos + 1;
1182  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1183  return MCDisassembler::Success;
1184}
1185
1186static DecodeStatus DecodeExtSize(MCInst &Inst,
1187                                  unsigned Insn,
1188                                  uint64_t Address,
1189                                  const void *Decoder) {
1190  int Size = (int) Insn  + 1;
1191  Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1192  return MCDisassembler::Success;
1193}
1194
1195static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1196                                     uint64_t Address, const void *Decoder) {
1197  Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1198  return MCDisassembler::Success;
1199}
1200