1//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an Mips MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsInstPrinter.h"
15#include "MCTargetDesc/MipsMCExpr.h"
16#include "MipsInstrInfo.h"
17#include "llvm/ADT/StringExtras.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCSymbol.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/raw_ostream.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28#define PRINT_ALIAS_INSTR
29#include "MipsGenAsmWriter.inc"
30
31template<unsigned R>
32static bool isReg(const MCInst &MI, unsigned OpNo) {
33  assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
34  return MI.getOperand(OpNo).getReg() == R;
35}
36
37const char* Mips::MipsFCCToString(Mips::CondCode CC) {
38  switch (CC) {
39  case FCOND_F:
40  case FCOND_T:   return "f";
41  case FCOND_UN:
42  case FCOND_OR:  return "un";
43  case FCOND_OEQ:
44  case FCOND_UNE: return "eq";
45  case FCOND_UEQ:
46  case FCOND_ONE: return "ueq";
47  case FCOND_OLT:
48  case FCOND_UGE: return "olt";
49  case FCOND_ULT:
50  case FCOND_OGE: return "ult";
51  case FCOND_OLE:
52  case FCOND_UGT: return "ole";
53  case FCOND_ULE:
54  case FCOND_OGT: return "ule";
55  case FCOND_SF:
56  case FCOND_ST:  return "sf";
57  case FCOND_NGLE:
58  case FCOND_GLE: return "ngle";
59  case FCOND_SEQ:
60  case FCOND_SNE: return "seq";
61  case FCOND_NGL:
62  case FCOND_GL:  return "ngl";
63  case FCOND_LT:
64  case FCOND_NLT: return "lt";
65  case FCOND_NGE:
66  case FCOND_GE:  return "nge";
67  case FCOND_LE:
68  case FCOND_NLE: return "le";
69  case FCOND_NGT:
70  case FCOND_GT:  return "ngt";
71  }
72  llvm_unreachable("Impossible condition code!");
73}
74
75void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
76  OS << '$' << StringRef(getRegisterName(RegNo)).lower();
77}
78
79void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
80                                StringRef Annot) {
81  switch (MI->getOpcode()) {
82  default:
83    break;
84  case Mips::RDHWR:
85  case Mips::RDHWR64:
86    O << "\t.set\tpush\n";
87    O << "\t.set\tmips32r2\n";
88    break;
89  case Mips::Save16:
90    O << "\tsave\t";
91    printSaveRestore(MI, O);
92    O << " # 16 bit inst\n";
93    return;
94  case Mips::SaveX16:
95    O << "\tsave\t";
96    printSaveRestore(MI, O);
97    O << "\n";
98    return;
99  case Mips::Restore16:
100    O << "\trestore\t";
101    printSaveRestore(MI, O);
102    O << " # 16 bit inst\n";
103    return;
104  case Mips::RestoreX16:
105    O << "\trestore\t";
106    printSaveRestore(MI, O);
107    O << "\n";
108    return;
109  }
110
111  // Try to print any aliases first.
112  if (!printAliasInstr(MI, O) && !printAlias(*MI, O))
113    printInstruction(MI, O);
114  printAnnotation(O, Annot);
115
116  switch (MI->getOpcode()) {
117  default:
118    break;
119  case Mips::RDHWR:
120  case Mips::RDHWR64:
121    O << "\n\t.set\tpop";
122  }
123}
124
125static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
126  int Offset = 0;
127  const MCSymbolRefExpr *SRE;
128
129  if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
130    SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
131    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS());
132    assert(SRE && CE && "Binary expression must be sym+const.");
133    Offset = CE->getValue();
134  } else if (const MipsMCExpr *ME = dyn_cast<MipsMCExpr>(Expr)) {
135    ME->print(OS);
136    return;
137  } else if (!(SRE = dyn_cast<MCSymbolRefExpr>(Expr)))
138    assert(false && "Unexpected MCExpr type.");
139
140  MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
141
142  switch (Kind) {
143  default:                                 llvm_unreachable("Invalid kind!");
144  case MCSymbolRefExpr::VK_None:           break;
145  case MCSymbolRefExpr::VK_Mips_GPREL:     OS << "%gp_rel("; break;
146  case MCSymbolRefExpr::VK_Mips_GOT_CALL:  OS << "%call16("; break;
147  case MCSymbolRefExpr::VK_Mips_GOT16:     OS << "%got(";    break;
148  case MCSymbolRefExpr::VK_Mips_GOT:       OS << "%got(";    break;
149  case MCSymbolRefExpr::VK_Mips_ABS_HI:    OS << "%hi(";     break;
150  case MCSymbolRefExpr::VK_Mips_ABS_LO:    OS << "%lo(";     break;
151  case MCSymbolRefExpr::VK_Mips_TLSGD:     OS << "%tlsgd(";  break;
152  case MCSymbolRefExpr::VK_Mips_TLSLDM:    OS << "%tlsldm(";  break;
153  case MCSymbolRefExpr::VK_Mips_DTPREL_HI: OS << "%dtprel_hi(";  break;
154  case MCSymbolRefExpr::VK_Mips_DTPREL_LO: OS << "%dtprel_lo(";  break;
155  case MCSymbolRefExpr::VK_Mips_GOTTPREL:  OS << "%gottprel("; break;
156  case MCSymbolRefExpr::VK_Mips_TPREL_HI:  OS << "%tprel_hi("; break;
157  case MCSymbolRefExpr::VK_Mips_TPREL_LO:  OS << "%tprel_lo("; break;
158  case MCSymbolRefExpr::VK_Mips_GPOFF_HI:  OS << "%hi(%neg(%gp_rel("; break;
159  case MCSymbolRefExpr::VK_Mips_GPOFF_LO:  OS << "%lo(%neg(%gp_rel("; break;
160  case MCSymbolRefExpr::VK_Mips_GOT_DISP:  OS << "%got_disp("; break;
161  case MCSymbolRefExpr::VK_Mips_GOT_PAGE:  OS << "%got_page("; break;
162  case MCSymbolRefExpr::VK_Mips_GOT_OFST:  OS << "%got_ofst("; break;
163  case MCSymbolRefExpr::VK_Mips_HIGHER:    OS << "%higher("; break;
164  case MCSymbolRefExpr::VK_Mips_HIGHEST:   OS << "%highest("; break;
165  case MCSymbolRefExpr::VK_Mips_GOT_HI16:  OS << "%got_hi("; break;
166  case MCSymbolRefExpr::VK_Mips_GOT_LO16:  OS << "%got_lo("; break;
167  case MCSymbolRefExpr::VK_Mips_CALL_HI16: OS << "%call_hi("; break;
168  case MCSymbolRefExpr::VK_Mips_CALL_LO16: OS << "%call_lo("; break;
169  case MCSymbolRefExpr::VK_Mips_PCREL_HI16: OS << "%pcrel_hi("; break;
170  case MCSymbolRefExpr::VK_Mips_PCREL_LO16: OS << "%pcrel_lo("; break;
171  }
172
173  OS << SRE->getSymbol();
174
175  if (Offset) {
176    if (Offset > 0)
177      OS << '+';
178    OS << Offset;
179  }
180
181  if ((Kind == MCSymbolRefExpr::VK_Mips_GPOFF_HI) ||
182      (Kind == MCSymbolRefExpr::VK_Mips_GPOFF_LO))
183    OS << ")))";
184  else if (Kind != MCSymbolRefExpr::VK_None)
185    OS << ')';
186}
187
188void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
189                                   raw_ostream &O) {
190  const MCOperand &Op = MI->getOperand(OpNo);
191  if (Op.isReg()) {
192    printRegName(O, Op.getReg());
193    return;
194  }
195
196  if (Op.isImm()) {
197    O << Op.getImm();
198    return;
199  }
200
201  assert(Op.isExpr() && "unknown operand kind in printOperand");
202  printExpr(Op.getExpr(), O);
203}
204
205void MipsInstPrinter::printUnsignedImm(const MCInst *MI, int opNum,
206                                       raw_ostream &O) {
207  const MCOperand &MO = MI->getOperand(opNum);
208  if (MO.isImm())
209    O << (unsigned short int)MO.getImm();
210  else
211    printOperand(MI, opNum, O);
212}
213
214void MipsInstPrinter::printUnsignedImm8(const MCInst *MI, int opNum,
215                                        raw_ostream &O) {
216  const MCOperand &MO = MI->getOperand(opNum);
217  if (MO.isImm())
218    O << (unsigned short int)(unsigned char)MO.getImm();
219  else
220    printOperand(MI, opNum, O);
221}
222
223void MipsInstPrinter::
224printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
225  // Load/Store memory operands -- imm($reg)
226  // If PIC target the target is loaded as the
227  // pattern lw $25,%call16($28)
228  printOperand(MI, opNum+1, O);
229  O << "(";
230  printOperand(MI, opNum, O);
231  O << ")";
232}
233
234void MipsInstPrinter::
235printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
236  // when using stack locations for not load/store instructions
237  // print the same way as all normal 3 operand instructions.
238  printOperand(MI, opNum, O);
239  O << ", ";
240  printOperand(MI, opNum+1, O);
241  return;
242}
243
244void MipsInstPrinter::
245printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
246  const MCOperand& MO = MI->getOperand(opNum);
247  O << MipsFCCToString((Mips::CondCode)MO.getImm());
248}
249
250void MipsInstPrinter::
251printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
252  llvm_unreachable("TODO");
253}
254
255bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
256                                 unsigned OpNo, raw_ostream &OS) {
257  OS << "\t" << Str << "\t";
258  printOperand(&MI, OpNo, OS);
259  return true;
260}
261
262bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
263                                 unsigned OpNo0, unsigned OpNo1,
264                                 raw_ostream &OS) {
265  printAlias(Str, MI, OpNo0, OS);
266  OS << ", ";
267  printOperand(&MI, OpNo1, OS);
268  return true;
269}
270
271bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
272  switch (MI.getOpcode()) {
273  case Mips::BEQ:
274    // beq $zero, $zero, $L2 => b $L2
275    // beq $r0, $zero, $L2 => beqz $r0, $L2
276    return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
277            printAlias("b", MI, 2, OS)) ||
278           (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
279  case Mips::BEQ64:
280    // beq $r0, $zero, $L2 => beqz $r0, $L2
281    return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
282  case Mips::BNE:
283    // bne $r0, $zero, $L2 => bnez $r0, $L2
284    return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
285  case Mips::BNE64:
286    // bne $r0, $zero, $L2 => bnez $r0, $L2
287    return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
288  case Mips::BGEZAL:
289    // bgezal $zero, $L1 => bal $L1
290    return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
291  case Mips::BC1T:
292    // bc1t $fcc0, $L1 => bc1t $L1
293    return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
294  case Mips::BC1F:
295    // bc1f $fcc0, $L1 => bc1f $L1
296    return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
297  case Mips::JALR:
298    // jalr $ra, $r1 => jalr $r1
299    return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
300  case Mips::JALR64:
301    // jalr $ra, $r1 => jalr $r1
302    return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
303  case Mips::NOR:
304  case Mips::NOR_MM:
305    // nor $r0, $r1, $zero => not $r0, $r1
306    return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
307  case Mips::NOR64:
308    // nor $r0, $r1, $zero => not $r0, $r1
309    return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
310  case Mips::OR:
311    // or $r0, $r1, $zero => move $r0, $r1
312    return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
313  default: return false;
314  }
315}
316
317void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
318  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
319    if (i != 0) O << ", ";
320    if (MI->getOperand(i).isReg())
321      printRegName(O, MI->getOperand(i).getReg());
322    else
323      printUnsignedImm(MI, i, O);
324  }
325}
326
327