MipsInstPrinter.cpp revision 93d995719e2459a6e9ccdb2c93a8ede8fa88c899
1//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class prints an Mips MCInst to a .s file. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "asm-printer" 15#include "MipsInstPrinter.h" 16#include "MipsInstrInfo.h" 17#include "llvm/ADT/StringExtras.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/MC/MCInstrInfo.h" 21#include "llvm/MC/MCSymbol.h" 22#include "llvm/Support/ErrorHandling.h" 23#include "llvm/Support/raw_ostream.h" 24using namespace llvm; 25 26#define PRINT_ALIAS_INSTR 27#include "MipsGenAsmWriter.inc" 28 29template<unsigned R> 30static bool isReg(const MCInst &MI, unsigned OpNo) { 31 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); 32 return MI.getOperand(OpNo).getReg() == R; 33} 34 35const char* Mips::MipsFCCToString(Mips::CondCode CC) { 36 switch (CC) { 37 case FCOND_F: 38 case FCOND_T: return "f"; 39 case FCOND_UN: 40 case FCOND_OR: return "un"; 41 case FCOND_OEQ: 42 case FCOND_UNE: return "eq"; 43 case FCOND_UEQ: 44 case FCOND_ONE: return "ueq"; 45 case FCOND_OLT: 46 case FCOND_UGE: return "olt"; 47 case FCOND_ULT: 48 case FCOND_OGE: return "ult"; 49 case FCOND_OLE: 50 case FCOND_UGT: return "ole"; 51 case FCOND_ULE: 52 case FCOND_OGT: return "ule"; 53 case FCOND_SF: 54 case FCOND_ST: return "sf"; 55 case FCOND_NGLE: 56 case FCOND_GLE: return "ngle"; 57 case FCOND_SEQ: 58 case FCOND_SNE: return "seq"; 59 case FCOND_NGL: 60 case FCOND_GL: return "ngl"; 61 case FCOND_LT: 62 case FCOND_NLT: return "lt"; 63 case FCOND_NGE: 64 case FCOND_GE: return "nge"; 65 case FCOND_LE: 66 case FCOND_NLE: return "le"; 67 case FCOND_NGT: 68 case FCOND_GT: return "ngt"; 69 } 70 llvm_unreachable("Impossible condition code!"); 71} 72 73void MipsInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 74 OS << '$' << StringRef(getRegisterName(RegNo)).lower(); 75} 76 77void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 78 StringRef Annot) { 79 switch (MI->getOpcode()) { 80 default: 81 break; 82 case Mips::RDHWR: 83 case Mips::RDHWR64: 84 O << "\t.set\tpush\n"; 85 O << "\t.set\tmips32r2\n"; 86 } 87 88 // Try to print any aliases first. 89 if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) 90 printInstruction(MI, O); 91 printAnnotation(O, Annot); 92 93 switch (MI->getOpcode()) { 94 default: 95 break; 96 case Mips::RDHWR: 97 case Mips::RDHWR64: 98 O << "\n\t.set\tpop"; 99 } 100} 101 102static void printExpr(const MCExpr *Expr, raw_ostream &OS) { 103 int Offset = 0; 104 const MCSymbolRefExpr *SRE; 105 106 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) { 107 SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS()); 108 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(BE->getRHS()); 109 assert(SRE && CE && "Binary expression must be sym+const."); 110 Offset = CE->getValue(); 111 } 112 else if (!(SRE = dyn_cast<MCSymbolRefExpr>(Expr))) 113 assert(false && "Unexpected MCExpr type."); 114 115 MCSymbolRefExpr::VariantKind Kind = SRE->getKind(); 116 117 switch (Kind) { 118 default: llvm_unreachable("Invalid kind!"); 119 case MCSymbolRefExpr::VK_None: break; 120 case MCSymbolRefExpr::VK_Mips_GPREL: OS << "%gp_rel("; break; 121 case MCSymbolRefExpr::VK_Mips_GOT_CALL: OS << "%call16("; break; 122 case MCSymbolRefExpr::VK_Mips_GOT16: OS << "%got("; break; 123 case MCSymbolRefExpr::VK_Mips_GOT: OS << "%got("; break; 124 case MCSymbolRefExpr::VK_Mips_ABS_HI: OS << "%hi("; break; 125 case MCSymbolRefExpr::VK_Mips_ABS_LO: OS << "%lo("; break; 126 case MCSymbolRefExpr::VK_Mips_TLSGD: OS << "%tlsgd("; break; 127 case MCSymbolRefExpr::VK_Mips_TLSLDM: OS << "%tlsldm("; break; 128 case MCSymbolRefExpr::VK_Mips_DTPREL_HI: OS << "%dtprel_hi("; break; 129 case MCSymbolRefExpr::VK_Mips_DTPREL_LO: OS << "%dtprel_lo("; break; 130 case MCSymbolRefExpr::VK_Mips_GOTTPREL: OS << "%gottprel("; break; 131 case MCSymbolRefExpr::VK_Mips_TPREL_HI: OS << "%tprel_hi("; break; 132 case MCSymbolRefExpr::VK_Mips_TPREL_LO: OS << "%tprel_lo("; break; 133 case MCSymbolRefExpr::VK_Mips_GPOFF_HI: OS << "%hi(%neg(%gp_rel("; break; 134 case MCSymbolRefExpr::VK_Mips_GPOFF_LO: OS << "%lo(%neg(%gp_rel("; break; 135 case MCSymbolRefExpr::VK_Mips_GOT_DISP: OS << "%got_disp("; break; 136 case MCSymbolRefExpr::VK_Mips_GOT_PAGE: OS << "%got_page("; break; 137 case MCSymbolRefExpr::VK_Mips_GOT_OFST: OS << "%got_ofst("; break; 138 case MCSymbolRefExpr::VK_Mips_HIGHER: OS << "%higher("; break; 139 case MCSymbolRefExpr::VK_Mips_HIGHEST: OS << "%highest("; break; 140 case MCSymbolRefExpr::VK_Mips_GOT_HI16: OS << "%got_hi("; break; 141 case MCSymbolRefExpr::VK_Mips_GOT_LO16: OS << "%got_lo("; break; 142 case MCSymbolRefExpr::VK_Mips_CALL_HI16: OS << "%call_hi("; break; 143 case MCSymbolRefExpr::VK_Mips_CALL_LO16: OS << "%call_lo("; break; 144 } 145 146 OS << SRE->getSymbol(); 147 148 if (Offset) { 149 if (Offset > 0) 150 OS << '+'; 151 OS << Offset; 152 } 153 154 if ((Kind == MCSymbolRefExpr::VK_Mips_GPOFF_HI) || 155 (Kind == MCSymbolRefExpr::VK_Mips_GPOFF_LO)) 156 OS << ")))"; 157 else if (Kind != MCSymbolRefExpr::VK_None) 158 OS << ')'; 159} 160 161void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 162 raw_ostream &O) { 163 const MCOperand &Op = MI->getOperand(OpNo); 164 if (Op.isReg()) { 165 printRegName(O, Op.getReg()); 166 return; 167 } 168 169 if (Op.isImm()) { 170 O << Op.getImm(); 171 return; 172 } 173 174 assert(Op.isExpr() && "unknown operand kind in printOperand"); 175 printExpr(Op.getExpr(), O); 176} 177 178void MipsInstPrinter::printUnsignedImm(const MCInst *MI, int opNum, 179 raw_ostream &O) { 180 const MCOperand &MO = MI->getOperand(opNum); 181 if (MO.isImm()) 182 O << (unsigned short int)MO.getImm(); 183 else 184 printOperand(MI, opNum, O); 185} 186 187void MipsInstPrinter:: 188printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) { 189 // Load/Store memory operands -- imm($reg) 190 // If PIC target the target is loaded as the 191 // pattern lw $25,%call16($28) 192 printOperand(MI, opNum+1, O); 193 O << "("; 194 printOperand(MI, opNum, O); 195 O << ")"; 196} 197 198void MipsInstPrinter:: 199printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) { 200 // when using stack locations for not load/store instructions 201 // print the same way as all normal 3 operand instructions. 202 printOperand(MI, opNum, O); 203 O << ", "; 204 printOperand(MI, opNum+1, O); 205 return; 206} 207 208void MipsInstPrinter:: 209printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { 210 const MCOperand& MO = MI->getOperand(opNum); 211 O << MipsFCCToString((Mips::CondCode)MO.getImm()); 212} 213 214void MipsInstPrinter:: 215printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) { 216 llvm_unreachable("TODO"); 217} 218 219bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, 220 unsigned OpNo, raw_ostream &OS) { 221 OS << "\t" << Str << "\t"; 222 printOperand(&MI, OpNo, OS); 223 return true; 224} 225 226bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI, 227 unsigned OpNo0, unsigned OpNo1, 228 raw_ostream &OS) { 229 printAlias(Str, MI, OpNo0, OS); 230 OS << ", "; 231 printOperand(&MI, OpNo1, OS); 232 return true; 233} 234 235bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) { 236 switch (MI.getOpcode()) { 237 case Mips::BEQ: 238 // beq $zero, $zero, $L2 => b $L2 239 // beq $r0, $zero, $L2 => beqz $r0, $L2 240 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && 241 printAlias("b", MI, 2, OS)) || 242 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); 243 case Mips::BEQ64: 244 // beq $r0, $zero, $L2 => beqz $r0, $L2 245 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); 246 case Mips::BNE: 247 // bne $r0, $zero, $L2 => bnez $r0, $L2 248 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); 249 case Mips::BNE64: 250 // bne $r0, $zero, $L2 => bnez $r0, $L2 251 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); 252 case Mips::BGEZAL: 253 // bgezal $zero, $L1 => bal $L1 254 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); 255 case Mips::BC1T: 256 // bc1t $fcc0, $L1 => bc1t $L1 257 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); 258 case Mips::BC1F: 259 // bc1f $fcc0, $L1 => bc1f $L1 260 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS); 261 case Mips::JALR: 262 // jalr $ra, $r1 => jalr $r1 263 return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS); 264 case Mips::JALR64: 265 // jalr $ra, $r1 => jalr $r1 266 return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS); 267 case Mips::NOR: 268 case Mips::NOR_MM: 269 // nor $r0, $r1, $zero => not $r0, $r1 270 return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS); 271 case Mips::NOR64: 272 // nor $r0, $r1, $zero => not $r0, $r1 273 return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS); 274 case Mips::OR: 275 // or $r0, $r1, $zero => move $r0, $r1 276 return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS); 277 default: return false; 278 } 279} 280