MipsAsmBackend.cpp revision 198ad916d736047f8a439f19dee25cee917df8a9 
1//===-- MipsASMBackend.cpp - Mips Asm Backend  ----------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "MipsFixupKinds.h"
16#include "MCTargetDesc/MipsMCTargetDesc.h"
17#include "llvm/MC/MCAsmBackend.h"
18#include "llvm/MC/MCAssembler.h"
19#include "llvm/MC/MCDirectives.h"
20#include "llvm/MC/MCELFObjectWriter.h"
21#include "llvm/MC/MCFixupKindInfo.h"
22#include "llvm/MC/MCObjectWriter.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26
27using namespace llvm;
28
29// Prepare value for the target space for it
30static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
31
32  // Add/subtract and shift
33  switch (Kind) {
34  default:
35    return 0;
36  case FK_GPRel_4:
37  case FK_Data_4:
38  case FK_Data_8:
39  case Mips::fixup_Mips_LO16:
40  case Mips::fixup_Mips_GPOFF_HI:
41  case Mips::fixup_Mips_GPOFF_LO:
42  case Mips::fixup_Mips_GOT_PAGE:
43  case Mips::fixup_Mips_GOT_OFST:
44  case Mips::fixup_Mips_GOT_DISP:
45  case Mips::fixup_Mips_GOT_LO16:
46  case Mips::fixup_Mips_CALL_LO16:
47    break;
48  case Mips::fixup_Mips_PC16:
49    // So far we are only using this type for branches.
50    // For branches we start 1 instruction after the branch
51    // so the displacement will be one instruction size less.
52    Value -= 4;
53    // The displacement is then divided by 4 to give us an 18 bit
54    // address range.
55    Value >>= 2;
56    break;
57  case Mips::fixup_Mips_26:
58    // So far we are only using this type for jumps.
59    // The displacement is then divided by 4 to give us an 28 bit
60    // address range.
61    Value >>= 2;
62    break;
63  case Mips::fixup_Mips_HI16:
64  case Mips::fixup_Mips_GOT_Local:
65  case Mips::fixup_Mips_GOT_HI16:
66  case Mips::fixup_Mips_CALL_HI16:
67    // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
68    Value = ((Value + 0x8000) >> 16) & 0xffff;
69    break;
70  case Mips::fixup_Mips_HIGHER:
71    // Get the 3rd 16-bits.
72    Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
73    break;
74  case Mips::fixup_Mips_HIGHEST:
75    // Get the 4th 16-bits.
76    Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
77    break;
78  }
79
80  return Value;
81}
82
83namespace {
84class MipsAsmBackend : public MCAsmBackend {
85  Triple::OSType OSType;
86  bool IsLittle; // Big or little endian
87  bool Is64Bit;  // 32 or 64 bit words
88
89public:
90  MipsAsmBackend(const Target &T,  Triple::OSType _OSType,
91                 bool _isLittle, bool _is64Bit)
92    :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
93
94  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
95    return createMipsELFObjectWriter(OS,
96      MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
97  }
98
99  /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
100  /// data fragment, at the offset specified by the fixup and following the
101  /// fixup kind as appropriate.
102  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
103                  uint64_t Value) const {
104    MCFixupKind Kind = Fixup.getKind();
105    Value = adjustFixupValue((unsigned)Kind, Value);
106
107    if (!Value)
108      return; // Doesn't change encoding.
109
110    // Where do we start in the object
111    unsigned Offset = Fixup.getOffset();
112    // Number of bytes we need to fixup
113    unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
114    // Used to point to big endian bytes
115    unsigned FullSize;
116
117    switch ((unsigned)Kind) {
118    case Mips::fixup_Mips_16:
119      FullSize = 2;
120      break;
121    case Mips::fixup_Mips_64:
122      FullSize = 8;
123      break;
124    default:
125      FullSize = 4;
126      break;
127    }
128
129    // Grab current value, if any, from bits.
130    uint64_t CurVal = 0;
131
132    for (unsigned i = 0; i != NumBytes; ++i) {
133      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
134      CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
135    }
136
137    uint64_t Mask = ((uint64_t)(-1) >>
138                     (64 - getFixupKindInfo(Kind).TargetSize));
139    CurVal |= Value & Mask;
140
141    // Write out the fixed up bytes back to the code/data bits.
142    for (unsigned i = 0; i != NumBytes; ++i) {
143      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
144      Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
145    }
146  }
147
148  unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
149
150  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
151    const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
152      // This table *must* be in same the order of fixup_* kinds in
153      // MipsFixupKinds.h.
154      //
155      // name                    offset  bits  flags
156      { "fixup_Mips_16",           0,     16,   0 },
157      { "fixup_Mips_32",           0,     32,   0 },
158      { "fixup_Mips_REL32",        0,     32,   0 },
159      { "fixup_Mips_26",           0,     26,   0 },
160      { "fixup_Mips_HI16",         0,     16,   0 },
161      { "fixup_Mips_LO16",         0,     16,   0 },
162      { "fixup_Mips_GPREL16",      0,     16,   0 },
163      { "fixup_Mips_LITERAL",      0,     16,   0 },
164      { "fixup_Mips_GOT_Global",   0,     16,   0 },
165      { "fixup_Mips_GOT_Local",    0,     16,   0 },
166      { "fixup_Mips_PC16",         0,     16,  MCFixupKindInfo::FKF_IsPCRel },
167      { "fixup_Mips_CALL16",       0,     16,   0 },
168      { "fixup_Mips_GPREL32",      0,     32,   0 },
169      { "fixup_Mips_SHIFT5",       6,      5,   0 },
170      { "fixup_Mips_SHIFT6",       6,      5,   0 },
171      { "fixup_Mips_64",           0,     64,   0 },
172      { "fixup_Mips_TLSGD",        0,     16,   0 },
173      { "fixup_Mips_GOTTPREL",     0,     16,   0 },
174      { "fixup_Mips_TPREL_HI",     0,     16,   0 },
175      { "fixup_Mips_TPREL_LO",     0,     16,   0 },
176      { "fixup_Mips_TLSLDM",       0,     16,   0 },
177      { "fixup_Mips_DTPREL_HI",    0,     16,   0 },
178      { "fixup_Mips_DTPREL_LO",    0,     16,   0 },
179      { "fixup_Mips_Branch_PCRel", 0,     16,  MCFixupKindInfo::FKF_IsPCRel },
180      { "fixup_Mips_GPOFF_HI",     0,     16,   0 },
181      { "fixup_Mips_GPOFF_LO",     0,     16,   0 },
182      { "fixup_Mips_GOT_PAGE",     0,     16,   0 },
183      { "fixup_Mips_GOT_OFST",     0,     16,   0 },
184      { "fixup_Mips_GOT_DISP",     0,     16,   0 },
185      { "fixup_Mips_HIGHER",       0,     16,   0 },
186      { "fixup_Mips_HIGHEST",      0,     16,   0 },
187      { "fixup_Mips_GOT_HI16",     0,     16,   0 },
188      { "fixup_Mips_GOT_LO16",     0,     16,   0 },
189      { "fixup_Mips_CALL_HI16",    0,     16,   0 },
190      { "fixup_Mips_CALL_LO16",    0,     16,   0 }
191    };
192
193    if (Kind < FirstTargetFixupKind)
194      return MCAsmBackend::getFixupKindInfo(Kind);
195
196    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
197           "Invalid kind!");
198    return Infos[Kind - FirstTargetFixupKind];
199  }
200
201  /// @name Target Relaxation Interfaces
202  /// @{
203
204  /// MayNeedRelaxation - Check whether the given instruction may need
205  /// relaxation.
206  ///
207  /// \param Inst - The instruction to test.
208  bool mayNeedRelaxation(const MCInst &Inst) const {
209    return false;
210  }
211
212  /// fixupNeedsRelaxation - Target specific predicate for whether a given
213  /// fixup requires the associated instruction to be relaxed.
214  bool fixupNeedsRelaxation(const MCFixup &Fixup,
215                            uint64_t Value,
216                            const MCInstFragment *DF,
217                            const MCAsmLayout &Layout) const {
218    // FIXME.
219    assert(0 && "RelaxInstruction() unimplemented");
220    return false;
221  }
222
223  /// RelaxInstruction - Relax the instruction in the given fragment
224  /// to the next wider instruction.
225  ///
226  /// \param Inst - The instruction to relax, which may be the same
227  /// as the output.
228  /// \param [out] Res On return, the relaxed instruction.
229  void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
230  }
231
232  /// @}
233
234  /// WriteNopData - Write an (optimal) nop sequence of Count bytes
235  /// to the given output. If the target cannot generate such a sequence,
236  /// it should return an error.
237  ///
238  /// \return - True on success.
239  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
240    // Check for a less than instruction size number of bytes
241    // FIXME: 16 bit instructions are not handled yet here.
242    // We shouldn't be using a hard coded number for instruction size.
243    if (Count % 4) return false;
244
245    uint64_t NumNops = Count / 4;
246    for (uint64_t i = 0; i != NumNops; ++i)
247      OW->Write32(0);
248    return true;
249  }
250}; // class MipsAsmBackend
251
252} // namespace
253
254// MCAsmBackend
255MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT,
256                                             StringRef CPU) {
257  return new MipsAsmBackend(T, Triple(TT).getOS(),
258                            /*IsLittle*/true, /*Is64Bit*/false);
259}
260
261MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT,
262                                             StringRef CPU) {
263  return new MipsAsmBackend(T, Triple(TT).getOS(),
264                            /*IsLittle*/false, /*Is64Bit*/false);
265}
266
267MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT,
268                                             StringRef CPU) {
269  return new MipsAsmBackend(T, Triple(TT).getOS(),
270                            /*IsLittle*/true, /*Is64Bit*/true);
271}
272
273MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT,
274                                             StringRef CPU) {
275  return new MipsAsmBackend(T, Triple(TT).getOS(),
276                            /*IsLittle*/false, /*Is64Bit*/true);
277}
278
279