MipsAsmBackend.cpp revision 1aaf43c2a2ec0fd4c8dbfe56558237219c5f8af7 
1//===-- MipsASMBackend.cpp - Mips Asm Backend  ----------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "MipsFixupKinds.h"
16#include "MCTargetDesc/MipsMCTargetDesc.h"
17#include "llvm/MC/MCAsmBackend.h"
18#include "llvm/MC/MCAssembler.h"
19#include "llvm/MC/MCDirectives.h"
20#include "llvm/MC/MCELFObjectWriter.h"
21#include "llvm/MC/MCFixupKindInfo.h"
22#include "llvm/MC/MCObjectWriter.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26
27using namespace llvm;
28
29// Prepare value for the target space for it
30static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
31
32  // Add/subtract and shift
33  switch (Kind) {
34  default:
35    return 0;
36  case FK_GPRel_4:
37  case FK_Data_4:
38  case FK_Data_8:
39  case Mips::fixup_Mips_LO16:
40  case Mips::fixup_Mips_GPREL16:
41  case Mips::fixup_Mips_GPOFF_HI:
42  case Mips::fixup_Mips_GPOFF_LO:
43  case Mips::fixup_Mips_GOT_PAGE:
44  case Mips::fixup_Mips_GOT_OFST:
45  case Mips::fixup_Mips_GOT_DISP:
46  case Mips::fixup_Mips_GOT_LO16:
47  case Mips::fixup_Mips_CALL_LO16:
48  case Mips::fixup_MICROMIPS_LO16:
49  case Mips::fixup_MICROMIPS_GOT_PAGE:
50  case Mips::fixup_MICROMIPS_GOT_OFST:
51  case Mips::fixup_MICROMIPS_GOT_DISP:
52    break;
53  case Mips::fixup_Mips_PC16:
54    // So far we are only using this type for branches.
55    // For branches we start 1 instruction after the branch
56    // so the displacement will be one instruction size less.
57    Value -= 4;
58    // The displacement is then divided by 4 to give us an 18 bit
59    // address range.
60    Value >>= 2;
61    break;
62  case Mips::fixup_Mips_26:
63    // So far we are only using this type for jumps.
64    // The displacement is then divided by 4 to give us an 28 bit
65    // address range.
66    Value >>= 2;
67    break;
68  case Mips::fixup_Mips_HI16:
69  case Mips::fixup_Mips_GOT_Local:
70  case Mips::fixup_Mips_GOT_HI16:
71  case Mips::fixup_Mips_CALL_HI16:
72  case Mips::fixup_MICROMIPS_HI16:
73    // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
74    Value = ((Value + 0x8000) >> 16) & 0xffff;
75    break;
76  case Mips::fixup_Mips_HIGHER:
77    // Get the 3rd 16-bits.
78    Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
79    break;
80  case Mips::fixup_Mips_HIGHEST:
81    // Get the 4th 16-bits.
82    Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
83    break;
84  case Mips::fixup_MICROMIPS_26_S1:
85    Value >>= 1;
86    break;
87  }
88
89  return Value;
90}
91
92namespace {
93class MipsAsmBackend : public MCAsmBackend {
94  Triple::OSType OSType;
95  bool IsLittle; // Big or little endian
96  bool Is64Bit;  // 32 or 64 bit words
97
98public:
99  MipsAsmBackend(const Target &T,  Triple::OSType _OSType,
100                 bool _isLittle, bool _is64Bit)
101    :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
102
103  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
104    return createMipsELFObjectWriter(OS,
105      MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
106  }
107
108  /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
109  /// data fragment, at the offset specified by the fixup and following the
110  /// fixup kind as appropriate.
111  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
112                  uint64_t Value) const {
113    MCFixupKind Kind = Fixup.getKind();
114    Value = adjustFixupValue((unsigned)Kind, Value);
115
116    if (!Value)
117      return; // Doesn't change encoding.
118
119    // Where do we start in the object
120    unsigned Offset = Fixup.getOffset();
121    // Number of bytes we need to fixup
122    unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
123    // Used to point to big endian bytes
124    unsigned FullSize;
125
126    switch ((unsigned)Kind) {
127    case Mips::fixup_Mips_16:
128      FullSize = 2;
129      break;
130    case Mips::fixup_Mips_64:
131      FullSize = 8;
132      break;
133    default:
134      FullSize = 4;
135      break;
136    }
137
138    // Grab current value, if any, from bits.
139    uint64_t CurVal = 0;
140
141    for (unsigned i = 0; i != NumBytes; ++i) {
142      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
143      CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
144    }
145
146    uint64_t Mask = ((uint64_t)(-1) >>
147                     (64 - getFixupKindInfo(Kind).TargetSize));
148    CurVal |= Value & Mask;
149
150    // Write out the fixed up bytes back to the code/data bits.
151    for (unsigned i = 0; i != NumBytes; ++i) {
152      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
153      Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
154    }
155  }
156
157  unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
158
159  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
160    const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
161      // This table *must* be in same the order of fixup_* kinds in
162      // MipsFixupKinds.h.
163      //
164      // name                    offset  bits  flags
165      { "fixup_Mips_16",           0,     16,   0 },
166      { "fixup_Mips_32",           0,     32,   0 },
167      { "fixup_Mips_REL32",        0,     32,   0 },
168      { "fixup_Mips_26",           0,     26,   0 },
169      { "fixup_Mips_HI16",         0,     16,   0 },
170      { "fixup_Mips_LO16",         0,     16,   0 },
171      { "fixup_Mips_GPREL16",      0,     16,   0 },
172      { "fixup_Mips_LITERAL",      0,     16,   0 },
173      { "fixup_Mips_GOT_Global",   0,     16,   0 },
174      { "fixup_Mips_GOT_Local",    0,     16,   0 },
175      { "fixup_Mips_PC16",         0,     16,  MCFixupKindInfo::FKF_IsPCRel },
176      { "fixup_Mips_CALL16",       0,     16,   0 },
177      { "fixup_Mips_GPREL32",      0,     32,   0 },
178      { "fixup_Mips_SHIFT5",       6,      5,   0 },
179      { "fixup_Mips_SHIFT6",       6,      5,   0 },
180      { "fixup_Mips_64",           0,     64,   0 },
181      { "fixup_Mips_TLSGD",        0,     16,   0 },
182      { "fixup_Mips_GOTTPREL",     0,     16,   0 },
183      { "fixup_Mips_TPREL_HI",     0,     16,   0 },
184      { "fixup_Mips_TPREL_LO",     0,     16,   0 },
185      { "fixup_Mips_TLSLDM",       0,     16,   0 },
186      { "fixup_Mips_DTPREL_HI",    0,     16,   0 },
187      { "fixup_Mips_DTPREL_LO",    0,     16,   0 },
188      { "fixup_Mips_Branch_PCRel", 0,     16,  MCFixupKindInfo::FKF_IsPCRel },
189      { "fixup_Mips_GPOFF_HI",     0,     16,   0 },
190      { "fixup_Mips_GPOFF_LO",     0,     16,   0 },
191      { "fixup_Mips_GOT_PAGE",     0,     16,   0 },
192      { "fixup_Mips_GOT_OFST",     0,     16,   0 },
193      { "fixup_Mips_GOT_DISP",     0,     16,   0 },
194      { "fixup_Mips_HIGHER",       0,     16,   0 },
195      { "fixup_Mips_HIGHEST",      0,     16,   0 },
196      { "fixup_Mips_GOT_HI16",     0,     16,   0 },
197      { "fixup_Mips_GOT_LO16",     0,     16,   0 },
198      { "fixup_Mips_CALL_HI16",    0,     16,   0 },
199      { "fixup_Mips_CALL_LO16",    0,     16,   0 },
200      { "fixup_MICROMIPS_26_S1",   0,     26,   0 },
201      { "fixup_MICROMIPS_HI16",    0,     16,   0 },
202      { "fixup_MICROMIPS_LO16",    0,     16,   0 },
203      { "fixup_MICROMIPS_GOT16",   0,     16,   0 },
204      { "fixup_MICROMIPS_CALL16",  0,     16,   0 },
205      { "fixup_MICROMIPS_GOT_DISP",        0,     16,   0 },
206      { "fixup_MICROMIPS_GOT_PAGE",        0,     16,   0 },
207      { "fixup_MICROMIPS_GOT_OFST",        0,     16,   0 },
208      { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0,     16,   0 },
209      { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0,     16,   0 },
210      { "fixup_MICROMIPS_TLS_TPREL_HI16",  0,     16,   0 },
211      { "fixup_MICROMIPS_TLS_TPREL_LO16",  0,     16,   0 }
212    };
213
214    if (Kind < FirstTargetFixupKind)
215      return MCAsmBackend::getFixupKindInfo(Kind);
216
217    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
218           "Invalid kind!");
219    return Infos[Kind - FirstTargetFixupKind];
220  }
221
222  /// @name Target Relaxation Interfaces
223  /// @{
224
225  /// MayNeedRelaxation - Check whether the given instruction may need
226  /// relaxation.
227  ///
228  /// \param Inst - The instruction to test.
229  bool mayNeedRelaxation(const MCInst &Inst) const {
230    return false;
231  }
232
233  /// fixupNeedsRelaxation - Target specific predicate for whether a given
234  /// fixup requires the associated instruction to be relaxed.
235  bool fixupNeedsRelaxation(const MCFixup &Fixup,
236                            uint64_t Value,
237                            const MCRelaxableFragment *DF,
238                            const MCAsmLayout &Layout) const {
239    // FIXME.
240    assert(0 && "RelaxInstruction() unimplemented");
241    return false;
242  }
243
244  /// RelaxInstruction - Relax the instruction in the given fragment
245  /// to the next wider instruction.
246  ///
247  /// \param Inst - The instruction to relax, which may be the same
248  /// as the output.
249  /// \param [out] Res On return, the relaxed instruction.
250  void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
251  }
252
253  /// @}
254
255  /// WriteNopData - Write an (optimal) nop sequence of Count bytes
256  /// to the given output. If the target cannot generate such a sequence,
257  /// it should return an error.
258  ///
259  /// \return - True on success.
260  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
261    // Check for a less than instruction size number of bytes
262    // FIXME: 16 bit instructions are not handled yet here.
263    // We shouldn't be using a hard coded number for instruction size.
264    if (Count % 4) return false;
265
266    uint64_t NumNops = Count / 4;
267    for (uint64_t i = 0; i != NumNops; ++i)
268      OW->Write32(0);
269    return true;
270  }
271}; // class MipsAsmBackend
272
273} // namespace
274
275// MCAsmBackend
276MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
277                                             const MCRegisterInfo &MRI,
278                                             StringRef TT,
279                                             StringRef CPU) {
280  return new MipsAsmBackend(T, Triple(TT).getOS(),
281                            /*IsLittle*/true, /*Is64Bit*/false);
282}
283
284MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
285                                             const MCRegisterInfo &MRI,
286                                             StringRef TT,
287                                             StringRef CPU) {
288  return new MipsAsmBackend(T, Triple(TT).getOS(),
289                            /*IsLittle*/false, /*Is64Bit*/false);
290}
291
292MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
293                                             const MCRegisterInfo &MRI,
294                                             StringRef TT,
295                                             StringRef CPU) {
296  return new MipsAsmBackend(T, Triple(TT).getOS(),
297                            /*IsLittle*/true, /*Is64Bit*/true);
298}
299
300MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
301                                             const MCRegisterInfo &MRI,
302                                             StringRef TT,
303                                             StringRef CPU) {
304  return new MipsAsmBackend(T, Triple(TT).getOS(),
305                            /*IsLittle*/false, /*Is64Bit*/true);
306}
307
308