MipsAsmBackend.cpp revision 5c042162beb3c2dd556e00aab84c4278a69cd5b1
1//===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the MipsAsmBackend and MipsELFObjectWriter classes. 11// 12//===----------------------------------------------------------------------===// 13// 14 15#include "MipsFixupKinds.h" 16#include "MCTargetDesc/MipsMCTargetDesc.h" 17#include "llvm/MC/MCAsmBackend.h" 18#include "llvm/MC/MCAssembler.h" 19#include "llvm/MC/MCDirectives.h" 20#include "llvm/MC/MCELFObjectWriter.h" 21#include "llvm/MC/MCFixupKindInfo.h" 22#include "llvm/MC/MCObjectWriter.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/raw_ostream.h" 26 27using namespace llvm; 28 29// Prepare value for the target space for it 30static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 31 32 // Add/subtract and shift 33 switch (Kind) { 34 default: 35 return 0; 36 case FK_GPRel_4: 37 case FK_Data_4: 38 case FK_Data_8: 39 case Mips::fixup_Mips_LO16: 40 case Mips::fixup_Mips_GPREL16: 41 case Mips::fixup_Mips_GPOFF_HI: 42 case Mips::fixup_Mips_GPOFF_LO: 43 case Mips::fixup_Mips_GOT_PAGE: 44 case Mips::fixup_Mips_GOT_OFST: 45 case Mips::fixup_Mips_GOT_DISP: 46 case Mips::fixup_Mips_GOT_LO16: 47 case Mips::fixup_Mips_CALL_LO16: 48 case Mips::fixup_MICROMIPS_LO16: 49 case Mips::fixup_MICROMIPS_GOT_PAGE: 50 case Mips::fixup_MICROMIPS_GOT_OFST: 51 case Mips::fixup_MICROMIPS_GOT_DISP: 52 break; 53 case Mips::fixup_Mips_PC16: 54 // So far we are only using this type for branches. 55 // For branches we start 1 instruction after the branch 56 // so the displacement will be one instruction size less. 57 Value -= 4; 58 // The displacement is then divided by 4 to give us an 18 bit 59 // address range. 60 Value >>= 2; 61 break; 62 case Mips::fixup_Mips_26: 63 // So far we are only using this type for jumps. 64 // The displacement is then divided by 4 to give us an 28 bit 65 // address range. 66 Value >>= 2; 67 break; 68 case Mips::fixup_Mips_HI16: 69 case Mips::fixup_Mips_GOT_Local: 70 case Mips::fixup_Mips_GOT_HI16: 71 case Mips::fixup_Mips_CALL_HI16: 72 case Mips::fixup_MICROMIPS_HI16: 73 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. 74 Value = ((Value + 0x8000) >> 16) & 0xffff; 75 break; 76 case Mips::fixup_Mips_HIGHER: 77 // Get the 3rd 16-bits. 78 Value = ((Value + 0x80008000LL) >> 32) & 0xffff; 79 break; 80 case Mips::fixup_Mips_HIGHEST: 81 // Get the 4th 16-bits. 82 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; 83 break; 84 case Mips::fixup_MICROMIPS_26_S1: 85 Value >>= 1; 86 break; 87 case Mips::fixup_MICROMIPS_PC16_S1: 88 Value -= 4; 89 Value >>= 1; 90 break; 91 } 92 93 return Value; 94} 95 96namespace { 97class MipsAsmBackend : public MCAsmBackend { 98 Triple::OSType OSType; 99 bool IsLittle; // Big or little endian 100 bool Is64Bit; // 32 or 64 bit words 101 102public: 103 MipsAsmBackend(const Target &T, Triple::OSType _OSType, 104 bool _isLittle, bool _is64Bit) 105 :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} 106 107 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 108 return createMipsELFObjectWriter(OS, 109 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); 110 } 111 112 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided 113 /// data fragment, at the offset specified by the fixup and following the 114 /// fixup kind as appropriate. 115 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 116 uint64_t Value) const { 117 MCFixupKind Kind = Fixup.getKind(); 118 Value = adjustFixupValue((unsigned)Kind, Value); 119 120 if (!Value) 121 return; // Doesn't change encoding. 122 123 // Where do we start in the object 124 unsigned Offset = Fixup.getOffset(); 125 // Number of bytes we need to fixup 126 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 127 // Used to point to big endian bytes 128 unsigned FullSize; 129 130 switch ((unsigned)Kind) { 131 case Mips::fixup_Mips_16: 132 FullSize = 2; 133 break; 134 case Mips::fixup_Mips_64: 135 FullSize = 8; 136 break; 137 default: 138 FullSize = 4; 139 break; 140 } 141 142 // Grab current value, if any, from bits. 143 uint64_t CurVal = 0; 144 145 for (unsigned i = 0; i != NumBytes; ++i) { 146 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 147 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 148 } 149 150 uint64_t Mask = ((uint64_t)(-1) >> 151 (64 - getFixupKindInfo(Kind).TargetSize)); 152 CurVal |= Value & Mask; 153 154 // Write out the fixed up bytes back to the code/data bits. 155 for (unsigned i = 0; i != NumBytes; ++i) { 156 unsigned Idx = IsLittle ? i : (FullSize - 1 - i); 157 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 158 } 159 } 160 161 unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } 162 163 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 164 const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { 165 // This table *must* be in same the order of fixup_* kinds in 166 // MipsFixupKinds.h. 167 // 168 // name offset bits flags 169 { "fixup_Mips_16", 0, 16, 0 }, 170 { "fixup_Mips_32", 0, 32, 0 }, 171 { "fixup_Mips_REL32", 0, 32, 0 }, 172 { "fixup_Mips_26", 0, 26, 0 }, 173 { "fixup_Mips_HI16", 0, 16, 0 }, 174 { "fixup_Mips_LO16", 0, 16, 0 }, 175 { "fixup_Mips_GPREL16", 0, 16, 0 }, 176 { "fixup_Mips_LITERAL", 0, 16, 0 }, 177 { "fixup_Mips_GOT_Global", 0, 16, 0 }, 178 { "fixup_Mips_GOT_Local", 0, 16, 0 }, 179 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 180 { "fixup_Mips_CALL16", 0, 16, 0 }, 181 { "fixup_Mips_GPREL32", 0, 32, 0 }, 182 { "fixup_Mips_SHIFT5", 6, 5, 0 }, 183 { "fixup_Mips_SHIFT6", 6, 5, 0 }, 184 { "fixup_Mips_64", 0, 64, 0 }, 185 { "fixup_Mips_TLSGD", 0, 16, 0 }, 186 { "fixup_Mips_GOTTPREL", 0, 16, 0 }, 187 { "fixup_Mips_TPREL_HI", 0, 16, 0 }, 188 { "fixup_Mips_TPREL_LO", 0, 16, 0 }, 189 { "fixup_Mips_TLSLDM", 0, 16, 0 }, 190 { "fixup_Mips_DTPREL_HI", 0, 16, 0 }, 191 { "fixup_Mips_DTPREL_LO", 0, 16, 0 }, 192 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 193 { "fixup_Mips_GPOFF_HI", 0, 16, 0 }, 194 { "fixup_Mips_GPOFF_LO", 0, 16, 0 }, 195 { "fixup_Mips_GOT_PAGE", 0, 16, 0 }, 196 { "fixup_Mips_GOT_OFST", 0, 16, 0 }, 197 { "fixup_Mips_GOT_DISP", 0, 16, 0 }, 198 { "fixup_Mips_HIGHER", 0, 16, 0 }, 199 { "fixup_Mips_HIGHEST", 0, 16, 0 }, 200 { "fixup_Mips_GOT_HI16", 0, 16, 0 }, 201 { "fixup_Mips_GOT_LO16", 0, 16, 0 }, 202 { "fixup_Mips_CALL_HI16", 0, 16, 0 }, 203 { "fixup_Mips_CALL_LO16", 0, 16, 0 }, 204 { "fixup_MICROMIPS_26_S1", 0, 26, 0 }, 205 { "fixup_MICROMIPS_HI16", 0, 16, 0 }, 206 { "fixup_MICROMIPS_LO16", 0, 16, 0 }, 207 { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, 208 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 209 { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, 210 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, 211 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 }, 212 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 }, 213 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, 214 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, 215 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, 216 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } 217 }; 218 219 if (Kind < FirstTargetFixupKind) 220 return MCAsmBackend::getFixupKindInfo(Kind); 221 222 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 223 "Invalid kind!"); 224 return Infos[Kind - FirstTargetFixupKind]; 225 } 226 227 /// @name Target Relaxation Interfaces 228 /// @{ 229 230 /// MayNeedRelaxation - Check whether the given instruction may need 231 /// relaxation. 232 /// 233 /// \param Inst - The instruction to test. 234 bool mayNeedRelaxation(const MCInst &Inst) const { 235 return false; 236 } 237 238 /// fixupNeedsRelaxation - Target specific predicate for whether a given 239 /// fixup requires the associated instruction to be relaxed. 240 bool fixupNeedsRelaxation(const MCFixup &Fixup, 241 uint64_t Value, 242 const MCRelaxableFragment *DF, 243 const MCAsmLayout &Layout) const { 244 // FIXME. 245 assert(0 && "RelaxInstruction() unimplemented"); 246 return false; 247 } 248 249 /// RelaxInstruction - Relax the instruction in the given fragment 250 /// to the next wider instruction. 251 /// 252 /// \param Inst - The instruction to relax, which may be the same 253 /// as the output. 254 /// \param [out] Res On return, the relaxed instruction. 255 void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 256 } 257 258 /// @} 259 260 /// WriteNopData - Write an (optimal) nop sequence of Count bytes 261 /// to the given output. If the target cannot generate such a sequence, 262 /// it should return an error. 263 /// 264 /// \return - True on success. 265 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 266 // Check for a less than instruction size number of bytes 267 // FIXME: 16 bit instructions are not handled yet here. 268 // We shouldn't be using a hard coded number for instruction size. 269 if (Count % 4) return false; 270 271 uint64_t NumNops = Count / 4; 272 for (uint64_t i = 0; i != NumNops; ++i) 273 OW->Write32(0); 274 return true; 275 } 276}; // class MipsAsmBackend 277 278} // namespace 279 280// MCAsmBackend 281MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, 282 const MCRegisterInfo &MRI, 283 StringRef TT, 284 StringRef CPU) { 285 return new MipsAsmBackend(T, Triple(TT).getOS(), 286 /*IsLittle*/true, /*Is64Bit*/false); 287} 288 289MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, 290 const MCRegisterInfo &MRI, 291 StringRef TT, 292 StringRef CPU) { 293 return new MipsAsmBackend(T, Triple(TT).getOS(), 294 /*IsLittle*/false, /*Is64Bit*/false); 295} 296 297MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, 298 const MCRegisterInfo &MRI, 299 StringRef TT, 300 StringRef CPU) { 301 return new MipsAsmBackend(T, Triple(TT).getOS(), 302 /*IsLittle*/true, /*Is64Bit*/true); 303} 304 305MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, 306 const MCRegisterInfo &MRI, 307 StringRef TT, 308 StringRef CPU) { 309 return new MipsAsmBackend(T, Triple(TT).getOS(), 310 /*IsLittle*/false, /*Is64Bit*/true); 311} 312 313