MipsAsmBackend.cpp revision 864f66085cd9543070ef01b9f7371c110ecd7898 
1//===-- MipsASMBackend.cpp - Mips Asm Backend  ----------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "MipsFixupKinds.h"
16#include "MCTargetDesc/MipsMCTargetDesc.h"
17#include "llvm/MC/MCAsmBackend.h"
18#include "llvm/MC/MCAssembler.h"
19#include "llvm/MC/MCDirectives.h"
20#include "llvm/MC/MCELFObjectWriter.h"
21#include "llvm/MC/MCFixupKindInfo.h"
22#include "llvm/MC/MCObjectWriter.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26
27using namespace llvm;
28
29// Prepare value for the target space for it
30static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
31
32  // Add/subtract and shift
33  switch (Kind) {
34  default:
35    return 0;
36  case FK_GPRel_4:
37  case FK_Data_4:
38  case Mips::fixup_Mips_LO16:
39    break;
40  case Mips::fixup_Mips_PC16:
41    // So far we are only using this type for branches.
42    // For branches we start 1 instruction after the branch
43    // so the displacement will be one instruction size less.
44    Value -= 4;
45    // The displacement is then divided by 4 to give us an 18 bit
46    // address range.
47    Value >>= 2;
48    break;
49  case Mips::fixup_Mips_26:
50    // So far we are only using this type for jumps.
51    // The displacement is then divided by 4 to give us an 28 bit
52    // address range.
53    Value >>= 2;
54    break;
55  case Mips::fixup_Mips_HI16:
56  case Mips::fixup_Mips_GOT_Local:
57    // Get the higher 16-bits. Also add 1 if bit 15 is 1.
58    Value = ((Value + 0x8000) >> 16) & 0xffff;
59    break;
60  }
61
62  return Value;
63}
64
65namespace {
66class MipsAsmBackend : public MCAsmBackend {
67  Triple::OSType OSType;
68  bool IsLittle; // Big or little endian
69  bool Is64Bit;  // 32 or 64 bit words
70
71public:
72  MipsAsmBackend(const Target &T,  Triple::OSType _OSType,
73                 bool _isLittle, bool _is64Bit)
74    :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
75
76  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
77    return createMipsELFObjectWriter(OS, OSType, IsLittle, Is64Bit);
78  }
79
80  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
81  /// data fragment, at the offset specified by the fixup and following the
82  /// fixup kind as appropriate.
83  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
84                  uint64_t Value) const {
85    MCFixupKind Kind = Fixup.getKind();
86    Value = adjustFixupValue((unsigned)Kind, Value);
87
88    if (!Value)
89      return; // Doesn't change encoding.
90
91    // Where do we start in the object
92    unsigned Offset = Fixup.getOffset();
93    // Number of bytes we need to fixup
94    unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
95    // Used to point to big endian bytes
96    unsigned FullSize;
97
98    switch ((unsigned)Kind) {
99    case Mips::fixup_Mips_16:
100      FullSize = 2;
101      break;
102    case Mips::fixup_Mips_64:
103      FullSize = 8;
104      break;
105    default:
106      FullSize = 4;
107      break;
108    }
109
110    // Grab current value, if any, from bits.
111    uint64_t CurVal = 0;
112
113    for (unsigned i = 0; i != NumBytes; ++i) {
114      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
115      CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
116    }
117
118    uint64_t Mask = ((uint64_t)(-1) >>
119                     (64 - getFixupKindInfo(Kind).TargetSize));
120    CurVal |= Value & Mask;
121
122    // Write out the fixed up bytes back to the code/data bits.
123    for (unsigned i = 0; i != NumBytes; ++i) {
124      unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
125      Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
126    }
127  }
128
129  unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
130
131  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
132    const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
133      // This table *must* be in same the order of fixup_* kinds in
134      // MipsFixupKinds.h.
135      //
136      // name                    offset  bits  flags
137      { "fixup_Mips_16",           0,     16,   0 },
138      { "fixup_Mips_32",           0,     32,   0 },
139      { "fixup_Mips_REL32",        0,     32,   0 },
140      { "fixup_Mips_26",           0,     26,   0 },
141      { "fixup_Mips_HI16",         0,     16,   0 },
142      { "fixup_Mips_LO16",         0,     16,   0 },
143      { "fixup_Mips_GPREL16",      0,     16,   0 },
144      { "fixup_Mips_LITERAL",      0,     16,   0 },
145      { "fixup_Mips_GOT_Global",   0,     16,   0 },
146      { "fixup_Mips_GOT_Local",    0,     16,   0 },
147      { "fixup_Mips_PC16",         0,     16,  MCFixupKindInfo::FKF_IsPCRel },
148      { "fixup_Mips_CALL16",       0,     16,   0 },
149      { "fixup_Mips_GPREL32",      0,     32,   0 },
150      { "fixup_Mips_SHIFT5",       6,      5,   0 },
151      { "fixup_Mips_SHIFT6",       6,      5,   0 },
152      { "fixup_Mips_64",           0,     64,   0 },
153      { "fixup_Mips_TLSGD",        0,     16,   0 },
154      { "fixup_Mips_GOTTPREL",     0,     16,   0 },
155      { "fixup_Mips_TPREL_HI",     0,     16,   0 },
156      { "fixup_Mips_TPREL_LO",     0,     16,   0 },
157      { "fixup_Mips_TLSLDM",       0,     16,   0 },
158      { "fixup_Mips_DTPREL_HI",    0,     16,   0 },
159      { "fixup_Mips_DTPREL_LO",    0,     16,   0 },
160      { "fixup_Mips_Branch_PCRel", 0,     16,  MCFixupKindInfo::FKF_IsPCRel }
161    };
162
163    if (Kind < FirstTargetFixupKind)
164      return MCAsmBackend::getFixupKindInfo(Kind);
165
166    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
167           "Invalid kind!");
168    return Infos[Kind - FirstTargetFixupKind];
169  }
170
171  /// @name Target Relaxation Interfaces
172  /// @{
173
174  /// MayNeedRelaxation - Check whether the given instruction may need
175  /// relaxation.
176  ///
177  /// \param Inst - The instruction to test.
178  bool mayNeedRelaxation(const MCInst &Inst) const {
179    return false;
180  }
181
182  /// fixupNeedsRelaxation - Target specific predicate for whether a given
183  /// fixup requires the associated instruction to be relaxed.
184  bool fixupNeedsRelaxation(const MCFixup &Fixup,
185                            uint64_t Value,
186                            const MCInstFragment *DF,
187                            const MCAsmLayout &Layout) const {
188    // FIXME.
189    assert(0 && "RelaxInstruction() unimplemented");
190    return false;
191  }
192
193  /// RelaxInstruction - Relax the instruction in the given fragment
194  /// to the next wider instruction.
195  ///
196  /// \param Inst - The instruction to relax, which may be the same
197  /// as the output.
198  /// \parm Res [output] - On return, the relaxed instruction.
199  void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
200  }
201
202  /// @}
203
204  /// WriteNopData - Write an (optimal) nop sequence of Count bytes
205  /// to the given output. If the target cannot generate such a sequence,
206  /// it should return an error.
207  ///
208  /// \return - True on success.
209  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
210    return true;
211  }
212}; // class MipsAsmBackend
213
214} // namespace
215
216// MCAsmBackend
217MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT) {
218  return new MipsAsmBackend(T, Triple(TT).getOS(),
219                            /*IsLittle*/true, /*Is64Bit*/false);
220}
221
222MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT) {
223  return new MipsAsmBackend(T, Triple(TT).getOS(),
224                            /*IsLittle*/false, /*Is64Bit*/false);
225}
226
227MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT) {
228  return new MipsAsmBackend(T, Triple(TT).getOS(),
229                            /*IsLittle*/true, /*Is64Bit*/true);
230}
231
232MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT) {
233  return new MipsAsmBackend(T, Triple(TT).getOS(),
234                            /*IsLittle*/false, /*Is64Bit*/true);
235}
236
237