MipsMCCodeEmitter.cpp revision 0140e55393c4403ab240c386501cdc5e438dcc0e 
1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13//
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "MCTargetDesc/MipsFixupKinds.h"
17#include "MCTargetDesc/MipsMCTargetDesc.h"
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30namespace {
31class MipsMCCodeEmitter : public MCCodeEmitter {
32  MipsMCCodeEmitter(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
33  void operator=(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
34  const MCInstrInfo &MCII;
35  const MCSubtargetInfo &STI;
36  MCContext &Ctx;
37  bool IsLittleEndian;
38
39public:
40  MipsMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
41                    MCContext &ctx, bool IsLittle) :
42            MCII(mcii), STI(sti) , Ctx(ctx), IsLittleEndian(IsLittle) {}
43
44  ~MipsMCCodeEmitter() {}
45
46  void EmitByte(unsigned char C, raw_ostream &OS) const {
47    OS << (char)C;
48  }
49
50  void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
51    // Output the instruction encoding in little endian byte order.
52    for (unsigned i = 0; i < Size; ++i) {
53      unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
54      EmitByte((Val >> Shift) & 0xff, OS);
55    }
56  }
57
58  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
59                         SmallVectorImpl<MCFixup> &Fixups) const;
60
61  // getBinaryCodeForInstr - TableGen'erated function for getting the
62  // binary encoding for an instruction.
63  uint64_t getBinaryCodeForInstr(const MCInst &MI,
64                                 SmallVectorImpl<MCFixup> &Fixups) const;
65
66  // getBranchJumpOpValue - Return binary encoding of the jump
67  // target operand. If the machine operand requires relocation,
68  // record the relocation and return zero.
69   unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
70                                 SmallVectorImpl<MCFixup> &Fixups) const;
71
72   // getBranchTargetOpValue - Return binary encoding of the branch
73   // target operand. If the machine operand requires relocation,
74   // record the relocation and return zero.
75  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
76                                  SmallVectorImpl<MCFixup> &Fixups) const;
77
78   // getMachineOpValue - Return binary encoding of operand. If the machin
79   // operand requires relocation, record the relocation and return zero.
80  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
81                             SmallVectorImpl<MCFixup> &Fixups) const;
82
83  unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
84                          SmallVectorImpl<MCFixup> &Fixups) const;
85  unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
86                              SmallVectorImpl<MCFixup> &Fixups) const;
87  unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
88                              SmallVectorImpl<MCFixup> &Fixups) const;
89
90}; // class MipsMCCodeEmitter
91}  // namespace
92
93MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
94                                               const MCRegisterInfo &MRI,
95                                               const MCSubtargetInfo &STI,
96                                               MCContext &Ctx)
97{
98  return new MipsMCCodeEmitter(MCII, STI, Ctx, false);
99}
100
101MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
102                                               const MCRegisterInfo &MRI,
103                                               const MCSubtargetInfo &STI,
104                                               MCContext &Ctx)
105{
106  return new MipsMCCodeEmitter(MCII, STI, Ctx, true);
107}
108
109/// EncodeInstruction - Emit the instruction.
110/// Size the instruction (currently only 4 bytes
111void MipsMCCodeEmitter::
112EncodeInstruction(const MCInst &MI, raw_ostream &OS,
113                  SmallVectorImpl<MCFixup> &Fixups) const
114{
115  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
116
117  // Check for unimplemented opcodes.
118  // Unfortunately in MIPS both NOT and SLL will come in with Binary == 0
119  // so we have to special check for them.
120  unsigned Opcode = MI.getOpcode();
121  if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
122    llvm_unreachable("unimplemented opcode in EncodeInstruction()");
123
124  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
125  uint64_t TSFlags = Desc.TSFlags;
126
127  // Pseudo instructions don't get encoded and shouldn't be here
128  // in the first place!
129  if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo)
130    llvm_unreachable("Pseudo opcode found in EncodeInstruction()");
131
132  // For now all instructions are 4 bytes
133  int Size = 4; // FIXME: Have Desc.getSize() return the correct value!
134
135  EmitInstruction(Binary, Size, OS);
136}
137
138/// getBranchTargetOpValue - Return binary encoding of the branch
139/// target operand. If the machine operand requires relocation,
140/// record the relocation and return zero.
141unsigned MipsMCCodeEmitter::
142getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
143                       SmallVectorImpl<MCFixup> &Fixups) const {
144
145  const MCOperand &MO = MI.getOperand(OpNo);
146  assert(MO.isExpr() && "getBranchTargetOpValue expects only expressions");
147
148  const MCExpr *Expr = MO.getExpr();
149  Fixups.push_back(MCFixup::Create(0, Expr,
150                                   MCFixupKind(Mips::fixup_Mips_PC16)));
151  return 0;
152}
153
154/// getJumpTargetOpValue - Return binary encoding of the jump
155/// target operand. If the machine operand requires relocation,
156/// record the relocation and return zero.
157unsigned MipsMCCodeEmitter::
158getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
159                     SmallVectorImpl<MCFixup> &Fixups) const {
160
161  const MCOperand &MO = MI.getOperand(OpNo);
162  assert(MO.isExpr() && "getJumpTargetOpValue expects only expressions");
163
164  const MCExpr *Expr = MO.getExpr();
165  Fixups.push_back(MCFixup::Create(0, Expr,
166                                   MCFixupKind(Mips::fixup_Mips_26)));
167  return 0;
168}
169
170/// getMachineOpValue - Return binary encoding of operand. If the machine
171/// operand requires relocation, record the relocation and return zero.
172unsigned MipsMCCodeEmitter::
173getMachineOpValue(const MCInst &MI, const MCOperand &MO,
174                  SmallVectorImpl<MCFixup> &Fixups) const {
175  if (MO.isReg()) {
176    unsigned Reg = MO.getReg();
177    unsigned RegNo = getMipsRegisterNumbering(Reg);
178    return RegNo;
179  } else if (MO.isImm()) {
180    return static_cast<unsigned>(MO.getImm());
181  } else if (MO.isFPImm()) {
182    return static_cast<unsigned>(APFloat(MO.getFPImm())
183        .bitcastToAPInt().getHiBits(32).getLimitedValue());
184  }
185
186  // MO must be an Expr.
187  assert(MO.isExpr());
188
189  const MCExpr *Expr = MO.getExpr();
190  MCExpr::ExprKind Kind = Expr->getKind();
191
192  if (Kind == MCExpr::Binary) {
193    Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();
194    Kind = Expr->getKind();
195  }
196
197  assert (Kind == MCExpr::SymbolRef);
198
199  Mips::Fixups FixupKind = Mips::Fixups(0);
200
201  switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
202  default: llvm_unreachable("Unknown fixup kind!");
203    break;
204  case MCSymbolRefExpr::VK_Mips_GOT_DISP :
205    llvm_unreachable("fixup kind VK_Mips_GOT_DISP not supported for direct object!");
206    break;
207  case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
208    FixupKind = Mips::fixup_Mips_GPOFF_HI;
209    break;
210  case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
211    FixupKind = Mips::fixup_Mips_GPOFF_LO;
212    break;
213  case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
214    FixupKind = Mips::fixup_Mips_GOT_PAGE;
215    break;
216  case MCSymbolRefExpr::VK_Mips_GOT_OFST :
217    FixupKind = Mips::fixup_Mips_GOT_OFST;
218    break;
219  case MCSymbolRefExpr::VK_Mips_GPREL:
220    FixupKind = Mips::fixup_Mips_GPREL16;
221    break;
222  case MCSymbolRefExpr::VK_Mips_GOT_CALL:
223    FixupKind = Mips::fixup_Mips_CALL16;
224    break;
225  case MCSymbolRefExpr::VK_Mips_GOT16:
226    FixupKind = Mips::fixup_Mips_GOT_Global;
227    break;
228  case MCSymbolRefExpr::VK_Mips_GOT:
229    FixupKind = Mips::fixup_Mips_GOT_Local;
230    break;
231  case MCSymbolRefExpr::VK_Mips_ABS_HI:
232    FixupKind = Mips::fixup_Mips_HI16;
233    break;
234  case MCSymbolRefExpr::VK_Mips_ABS_LO:
235    FixupKind = Mips::fixup_Mips_LO16;
236    break;
237  case MCSymbolRefExpr::VK_Mips_TLSGD:
238    FixupKind = Mips::fixup_Mips_TLSGD;
239    break;
240  case MCSymbolRefExpr::VK_Mips_TLSLDM:
241    FixupKind = Mips::fixup_Mips_TLSLDM;
242    break;
243  case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
244    FixupKind = Mips::fixup_Mips_DTPREL_HI;
245    break;
246  case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
247    FixupKind = Mips::fixup_Mips_DTPREL_LO;
248    break;
249  case MCSymbolRefExpr::VK_Mips_GOTTPREL:
250    FixupKind = Mips::fixup_Mips_GOTTPREL;
251    break;
252  case MCSymbolRefExpr::VK_Mips_TPREL_HI:
253    FixupKind = Mips::fixup_Mips_TPREL_HI;
254    break;
255  case MCSymbolRefExpr::VK_Mips_TPREL_LO:
256    FixupKind = Mips::fixup_Mips_TPREL_LO;
257    break;
258  } // switch
259
260  Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind)));
261
262  // All of the information is in the fixup.
263  return 0;
264}
265
266/// getMemEncoding - Return binary encoding of memory related operand.
267/// If the offset operand requires relocation, record the relocation.
268unsigned
269MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
270                                  SmallVectorImpl<MCFixup> &Fixups) const {
271  // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
272  assert(MI.getOperand(OpNo).isReg());
273  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
274  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
275
276  return (OffBits & 0xFFFF) | RegBits;
277}
278
279unsigned
280MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
281                                      SmallVectorImpl<MCFixup> &Fixups) const {
282  assert(MI.getOperand(OpNo).isImm());
283  unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
284  return SizeEncoding - 1;
285}
286
287// FIXME: should be called getMSBEncoding
288//
289unsigned
290MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
291                                      SmallVectorImpl<MCFixup> &Fixups) const {
292  assert(MI.getOperand(OpNo-1).isImm());
293  assert(MI.getOperand(OpNo).isImm());
294  unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
295  unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
296
297  return Position + Size - 1;
298}
299
300#include "MipsGenMCCodeEmitter.inc"
301
302