MipsMCCodeEmitter.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#define DEBUG_TYPE "mccodeemitter"
16
17#include "MipsMCCodeEmitter.h"
18#include "MCTargetDesc/MipsFixupKinds.h"
19#include "MCTargetDesc/MipsMCExpr.h"
20#include "MCTargetDesc/MipsMCTargetDesc.h"
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/MC/MCFixup.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/Support/raw_ostream.h"
30
31#define GET_INSTRMAP_INFO
32#include "MipsGenInstrInfo.inc"
33#undef GET_INSTRMAP_INFO
34
35namespace llvm {
36MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37                                         const MCRegisterInfo &MRI,
38                                         const MCSubtargetInfo &STI,
39                                         MCContext &Ctx) {
40  return new MipsMCCodeEmitter(MCII, Ctx, false);
41}
42
43MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
44                                         const MCRegisterInfo &MRI,
45                                         const MCSubtargetInfo &STI,
46                                         MCContext &Ctx) {
47  return new MipsMCCodeEmitter(MCII, Ctx, true);
48}
49} // End of namespace llvm.
50
51// If the D<shift> instruction has a shift amount that is greater
52// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
53static void LowerLargeShift(MCInst& Inst) {
54
55  assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!");
56  assert(Inst.getOperand(2).isImm());
57
58  int64_t Shift = Inst.getOperand(2).getImm();
59  if (Shift <= 31)
60    return; // Do nothing
61  Shift -= 32;
62
63  // saminus32
64  Inst.getOperand(2).setImm(Shift);
65
66  switch (Inst.getOpcode()) {
67  default:
68    // Calling function is not synchronized
69    llvm_unreachable("Unexpected shift instruction");
70  case Mips::DSLL:
71    Inst.setOpcode(Mips::DSLL32);
72    return;
73  case Mips::DSRL:
74    Inst.setOpcode(Mips::DSRL32);
75    return;
76  case Mips::DSRA:
77    Inst.setOpcode(Mips::DSRA32);
78    return;
79  case Mips::DROTR:
80    Inst.setOpcode(Mips::DROTR32);
81    return;
82  }
83}
84
85// Pick a DEXT or DINS instruction variant based on the pos and size operands
86static void LowerDextDins(MCInst& InstIn) {
87  int Opcode = InstIn.getOpcode();
88
89  if (Opcode == Mips::DEXT)
90    assert(InstIn.getNumOperands() == 4 &&
91           "Invalid no. of machine operands for DEXT!");
92  else // Only DEXT and DINS are possible
93    assert(InstIn.getNumOperands() == 5 &&
94           "Invalid no. of machine operands for DINS!");
95
96  assert(InstIn.getOperand(2).isImm());
97  int64_t pos = InstIn.getOperand(2).getImm();
98  assert(InstIn.getOperand(3).isImm());
99  int64_t size = InstIn.getOperand(3).getImm();
100
101  if (size <= 32) {
102    if (pos < 32)  // DEXT/DINS, do nothing
103      return;
104    // DEXTU/DINSU
105    InstIn.getOperand(2).setImm(pos - 32);
106    InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU);
107    return;
108  }
109  // DEXTM/DINSM
110  assert(pos < 32 && "DEXT/DINS cannot have both size and pos > 32");
111  InstIn.getOperand(3).setImm(size - 32);
112  InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
113  return;
114}
115
116bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
117  return STI.getFeatureBits() & Mips::FeatureMicroMips;
118}
119
120void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
121  OS << (char)C;
122}
123
124void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
125                                        const MCSubtargetInfo &STI,
126                                        raw_ostream &OS) const {
127  // Output the instruction encoding in little endian byte order.
128  // Little-endian byte ordering:
129  //   mips32r2:   4 | 3 | 2 | 1
130  //   microMIPS:  2 | 1 | 4 | 3
131  if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
132    EmitInstruction(Val >> 16, 2, STI, OS);
133    EmitInstruction(Val, 2, STI, OS);
134  } else {
135    for (unsigned i = 0; i < Size; ++i) {
136      unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
137      EmitByte((Val >> Shift) & 0xff, OS);
138    }
139  }
140}
141
142/// EncodeInstruction - Emit the instruction.
143/// Size the instruction with Desc.getSize().
144void MipsMCCodeEmitter::
145EncodeInstruction(const MCInst &MI, raw_ostream &OS,
146                  SmallVectorImpl<MCFixup> &Fixups,
147                  const MCSubtargetInfo &STI) const
148{
149
150  // Non-pseudo instructions that get changed for direct object
151  // only based on operand values.
152  // If this list of instructions get much longer we will move
153  // the check to a function call. Until then, this is more efficient.
154  MCInst TmpInst = MI;
155  switch (MI.getOpcode()) {
156  // If shift amount is >= 32 it the inst needs to be lowered further
157  case Mips::DSLL:
158  case Mips::DSRL:
159  case Mips::DSRA:
160  case Mips::DROTR:
161    LowerLargeShift(TmpInst);
162    break;
163    // Double extract instruction is chosen by pos and size operands
164  case Mips::DEXT:
165  case Mips::DINS:
166    LowerDextDins(TmpInst);
167  }
168
169  unsigned long N = Fixups.size();
170  uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
171
172  // Check for unimplemented opcodes.
173  // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
174  // so we have to special check for them.
175  unsigned Opcode = TmpInst.getOpcode();
176  if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
177    llvm_unreachable("unimplemented opcode in EncodeInstruction()");
178
179  if (STI.getFeatureBits() & Mips::FeatureMicroMips) {
180    int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips);
181    if (NewOpcode != -1) {
182      if (Fixups.size() > N)
183        Fixups.pop_back();
184      Opcode = NewOpcode;
185      TmpInst.setOpcode (NewOpcode);
186      Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
187    }
188  }
189
190  const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
191
192  // Get byte count of instruction
193  unsigned Size = Desc.getSize();
194  if (!Size)
195    llvm_unreachable("Desc.getSize() returns 0");
196
197  EmitInstruction(Binary, Size, STI, OS);
198}
199
200/// getBranchTargetOpValue - Return binary encoding of the branch
201/// target operand. If the machine operand requires relocation,
202/// record the relocation and return zero.
203unsigned MipsMCCodeEmitter::
204getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
205                       SmallVectorImpl<MCFixup> &Fixups,
206                       const MCSubtargetInfo &STI) const {
207
208  const MCOperand &MO = MI.getOperand(OpNo);
209
210  // If the destination is an immediate, divide by 4.
211  if (MO.isImm()) return MO.getImm() >> 2;
212
213  assert(MO.isExpr() &&
214         "getBranchTargetOpValue expects only expressions or immediates");
215
216  const MCExpr *Expr = MO.getExpr();
217  Fixups.push_back(MCFixup::Create(0, Expr,
218                                   MCFixupKind(Mips::fixup_Mips_PC16)));
219  return 0;
220}
221
222/// getBranchTargetOpValue - Return binary encoding of the microMIPS branch
223/// target operand. If the machine operand requires relocation,
224/// record the relocation and return zero.
225unsigned MipsMCCodeEmitter::
226getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
227                         SmallVectorImpl<MCFixup> &Fixups,
228                         const MCSubtargetInfo &STI) const {
229
230  const MCOperand &MO = MI.getOperand(OpNo);
231
232  // If the destination is an immediate, divide by 2.
233  if (MO.isImm()) return MO.getImm() >> 1;
234
235  assert(MO.isExpr() &&
236         "getBranchTargetOpValueMM expects only expressions or immediates");
237
238  const MCExpr *Expr = MO.getExpr();
239  Fixups.push_back(MCFixup::Create(0, Expr,
240                   MCFixupKind(Mips::
241                               fixup_MICROMIPS_PC16_S1)));
242  return 0;
243}
244
245/// getJumpTargetOpValue - Return binary encoding of the jump
246/// target operand. If the machine operand requires relocation,
247/// record the relocation and return zero.
248unsigned MipsMCCodeEmitter::
249getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
250                     SmallVectorImpl<MCFixup> &Fixups,
251                     const MCSubtargetInfo &STI) const {
252
253  const MCOperand &MO = MI.getOperand(OpNo);
254  // If the destination is an immediate, divide by 4.
255  if (MO.isImm()) return MO.getImm()>>2;
256
257  assert(MO.isExpr() &&
258         "getJumpTargetOpValue expects only expressions or an immediate");
259
260  const MCExpr *Expr = MO.getExpr();
261  Fixups.push_back(MCFixup::Create(0, Expr,
262                                   MCFixupKind(Mips::fixup_Mips_26)));
263  return 0;
264}
265
266unsigned MipsMCCodeEmitter::
267getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
268                       SmallVectorImpl<MCFixup> &Fixups,
269                       const MCSubtargetInfo &STI) const {
270
271  const MCOperand &MO = MI.getOperand(OpNo);
272  // If the destination is an immediate, divide by 2.
273  if (MO.isImm()) return MO.getImm() >> 1;
274
275  assert(MO.isExpr() &&
276         "getJumpTargetOpValueMM expects only expressions or an immediate");
277
278  const MCExpr *Expr = MO.getExpr();
279  Fixups.push_back(MCFixup::Create(0, Expr,
280                                   MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
281  return 0;
282}
283
284unsigned MipsMCCodeEmitter::
285getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups,
286               const MCSubtargetInfo &STI) const {
287  int64_t Res;
288
289  if (Expr->EvaluateAsAbsolute(Res))
290    return Res;
291
292  MCExpr::ExprKind Kind = Expr->getKind();
293  if (Kind == MCExpr::Constant) {
294    return cast<MCConstantExpr>(Expr)->getValue();
295  }
296
297  if (Kind == MCExpr::Binary) {
298    unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
299    Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
300    return Res;
301  }
302
303  if (Kind == MCExpr::Target) {
304    const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
305
306    Mips::Fixups FixupKind = Mips::Fixups(0);
307    switch (MipsExpr->getKind()) {
308    default: llvm_unreachable("Unsupported fixup kind for target expression!");
309    case MipsMCExpr::VK_Mips_HIGHEST:
310      FixupKind = Mips::fixup_Mips_HIGHEST;
311      break;
312    case MipsMCExpr::VK_Mips_HIGHER:
313      FixupKind = Mips::fixup_Mips_HIGHER;
314      break;
315    case MipsMCExpr::VK_Mips_HI:
316      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
317                                   : Mips::fixup_Mips_HI16;
318      break;
319    case MipsMCExpr::VK_Mips_LO:
320      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
321                                   : Mips::fixup_Mips_LO16;
322      break;
323    }
324    Fixups.push_back(MCFixup::Create(0, MipsExpr, MCFixupKind(FixupKind)));
325    return 0;
326  }
327
328  if (Kind == MCExpr::SymbolRef) {
329    Mips::Fixups FixupKind = Mips::Fixups(0);
330
331    switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
332    default: llvm_unreachable("Unknown fixup kind!");
333      break;
334    case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
335      FixupKind = Mips::fixup_Mips_GPOFF_HI;
336      break;
337    case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
338      FixupKind = Mips::fixup_Mips_GPOFF_LO;
339      break;
340    case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
341      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
342                              : Mips::fixup_Mips_GOT_PAGE;
343      break;
344    case MCSymbolRefExpr::VK_Mips_GOT_OFST :
345      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
346                              : Mips::fixup_Mips_GOT_OFST;
347      break;
348    case MCSymbolRefExpr::VK_Mips_GOT_DISP :
349      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
350                              : Mips::fixup_Mips_GOT_DISP;
351      break;
352    case MCSymbolRefExpr::VK_Mips_GPREL:
353      FixupKind = Mips::fixup_Mips_GPREL16;
354      break;
355    case MCSymbolRefExpr::VK_Mips_GOT_CALL:
356      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
357                              : Mips::fixup_Mips_CALL16;
358      break;
359    case MCSymbolRefExpr::VK_Mips_GOT16:
360      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
361                              : Mips::fixup_Mips_GOT_Global;
362      break;
363    case MCSymbolRefExpr::VK_Mips_GOT:
364      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
365                              : Mips::fixup_Mips_GOT_Local;
366      break;
367    case MCSymbolRefExpr::VK_Mips_ABS_HI:
368      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
369                              : Mips::fixup_Mips_HI16;
370      break;
371    case MCSymbolRefExpr::VK_Mips_ABS_LO:
372      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
373                              : Mips::fixup_Mips_LO16;
374      break;
375    case MCSymbolRefExpr::VK_Mips_TLSGD:
376      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
377                              : Mips::fixup_Mips_TLSGD;
378      break;
379    case MCSymbolRefExpr::VK_Mips_TLSLDM:
380      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
381                              : Mips::fixup_Mips_TLSLDM;
382      break;
383    case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
384      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
385                              : Mips::fixup_Mips_DTPREL_HI;
386      break;
387    case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
388      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
389                              : Mips::fixup_Mips_DTPREL_LO;
390      break;
391    case MCSymbolRefExpr::VK_Mips_GOTTPREL:
392      FixupKind = Mips::fixup_Mips_GOTTPREL;
393      break;
394    case MCSymbolRefExpr::VK_Mips_TPREL_HI:
395      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
396                              : Mips::fixup_Mips_TPREL_HI;
397      break;
398    case MCSymbolRefExpr::VK_Mips_TPREL_LO:
399      FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
400                              : Mips::fixup_Mips_TPREL_LO;
401      break;
402    case MCSymbolRefExpr::VK_Mips_HIGHER:
403      FixupKind = Mips::fixup_Mips_HIGHER;
404      break;
405    case MCSymbolRefExpr::VK_Mips_HIGHEST:
406      FixupKind = Mips::fixup_Mips_HIGHEST;
407      break;
408    case MCSymbolRefExpr::VK_Mips_GOT_HI16:
409      FixupKind = Mips::fixup_Mips_GOT_HI16;
410      break;
411    case MCSymbolRefExpr::VK_Mips_GOT_LO16:
412      FixupKind = Mips::fixup_Mips_GOT_LO16;
413      break;
414    case MCSymbolRefExpr::VK_Mips_CALL_HI16:
415      FixupKind = Mips::fixup_Mips_CALL_HI16;
416      break;
417    case MCSymbolRefExpr::VK_Mips_CALL_LO16:
418      FixupKind = Mips::fixup_Mips_CALL_LO16;
419      break;
420    } // switch
421
422    Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
423    return 0;
424  }
425  return 0;
426}
427
428/// getMachineOpValue - Return binary encoding of operand. If the machine
429/// operand requires relocation, record the relocation and return zero.
430unsigned MipsMCCodeEmitter::
431getMachineOpValue(const MCInst &MI, const MCOperand &MO,
432                  SmallVectorImpl<MCFixup> &Fixups,
433                  const MCSubtargetInfo &STI) const {
434  if (MO.isReg()) {
435    unsigned Reg = MO.getReg();
436    unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
437    return RegNo;
438  } else if (MO.isImm()) {
439    return static_cast<unsigned>(MO.getImm());
440  } else if (MO.isFPImm()) {
441    return static_cast<unsigned>(APFloat(MO.getFPImm())
442        .bitcastToAPInt().getHiBits(32).getLimitedValue());
443  }
444  // MO must be an Expr.
445  assert(MO.isExpr());
446  return getExprOpValue(MO.getExpr(),Fixups, STI);
447}
448
449/// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
450/// instructions.
451unsigned
452MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
453                                     SmallVectorImpl<MCFixup> &Fixups,
454                                     const MCSubtargetInfo &STI) const {
455  // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
456  assert(MI.getOperand(OpNo).isReg());
457  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
458  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
459
460  // The immediate field of an LD/ST instruction is scaled which means it must
461  // be divided (when encoding) by the size (in bytes) of the instructions'
462  // data format.
463  // .b - 1 byte
464  // .h - 2 bytes
465  // .w - 4 bytes
466  // .d - 8 bytes
467  switch(MI.getOpcode())
468  {
469  default:
470    assert (0 && "Unexpected instruction");
471    break;
472  case Mips::LD_B:
473  case Mips::ST_B:
474    // We don't need to scale the offset in this case
475    break;
476  case Mips::LD_H:
477  case Mips::ST_H:
478    OffBits >>= 1;
479    break;
480  case Mips::LD_W:
481  case Mips::ST_W:
482    OffBits >>= 2;
483    break;
484  case Mips::LD_D:
485  case Mips::ST_D:
486    OffBits >>= 3;
487    break;
488  }
489
490  return (OffBits & 0xFFFF) | RegBits;
491}
492
493/// getMemEncoding - Return binary encoding of memory related operand.
494/// If the offset operand requires relocation, record the relocation.
495unsigned
496MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
497                                  SmallVectorImpl<MCFixup> &Fixups,
498                                  const MCSubtargetInfo &STI) const {
499  // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
500  assert(MI.getOperand(OpNo).isReg());
501  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
502  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
503
504  return (OffBits & 0xFFFF) | RegBits;
505}
506
507unsigned MipsMCCodeEmitter::
508getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
509                      SmallVectorImpl<MCFixup> &Fixups,
510                      const MCSubtargetInfo &STI) const {
511  // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
512  assert(MI.getOperand(OpNo).isReg());
513  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
514  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
515
516  return (OffBits & 0x0FFF) | RegBits;
517}
518
519unsigned
520MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
521                                      SmallVectorImpl<MCFixup> &Fixups,
522                                      const MCSubtargetInfo &STI) const {
523  assert(MI.getOperand(OpNo).isImm());
524  unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
525  return SizeEncoding - 1;
526}
527
528// FIXME: should be called getMSBEncoding
529//
530unsigned
531MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
532                                      SmallVectorImpl<MCFixup> &Fixups,
533                                      const MCSubtargetInfo &STI) const {
534  assert(MI.getOperand(OpNo-1).isImm());
535  assert(MI.getOperand(OpNo).isImm());
536  unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
537  unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
538
539  return Position + Size - 1;
540}
541
542unsigned
543MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
544                                     SmallVectorImpl<MCFixup> &Fixups,
545                                     const MCSubtargetInfo &STI) const {
546  assert(MI.getOperand(OpNo).isImm());
547  // The immediate is encoded as 'immediate - 1'.
548  return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1;
549}
550
551#include "MipsGenMCCodeEmitter.inc"
552
553