MipsMCCodeEmitter.cpp revision 8e71e617c9b1e42737ffd00984a5025ec90c734c 
1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13//
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "MCTargetDesc/MipsDirectObjLower.h"
17#include "MCTargetDesc/MipsFixupKinds.h"
18#include "MCTargetDesc/MipsMCTargetDesc.h"
19#include "llvm/ADT/APFloat.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/Support/raw_ostream.h"
28
29using namespace llvm;
30
31namespace {
32class MipsMCCodeEmitter : public MCCodeEmitter {
33  MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
34  void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35  const MCInstrInfo &MCII;
36  bool IsLittleEndian;
37
38public:
39  MipsMCCodeEmitter(const MCInstrInfo &mcii, bool IsLittle) :
40            MCII(mcii), IsLittleEndian(IsLittle) {}
41
42  ~MipsMCCodeEmitter() {}
43
44  void EmitByte(unsigned char C, raw_ostream &OS) const {
45    OS << (char)C;
46  }
47
48  void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
49    // Output the instruction encoding in little endian byte order.
50    for (unsigned i = 0; i < Size; ++i) {
51      unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
52      EmitByte((Val >> Shift) & 0xff, OS);
53    }
54  }
55
56  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57                         SmallVectorImpl<MCFixup> &Fixups) const;
58
59  // getBinaryCodeForInstr - TableGen'erated function for getting the
60  // binary encoding for an instruction.
61  uint64_t getBinaryCodeForInstr(const MCInst &MI,
62                                 SmallVectorImpl<MCFixup> &Fixups) const;
63
64  // getBranchJumpOpValue - Return binary encoding of the jump
65  // target operand. If the machine operand requires relocation,
66  // record the relocation and return zero.
67   unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
68                                 SmallVectorImpl<MCFixup> &Fixups) const;
69
70   // getBranchTargetOpValue - Return binary encoding of the branch
71   // target operand. If the machine operand requires relocation,
72   // record the relocation and return zero.
73  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
74                                  SmallVectorImpl<MCFixup> &Fixups) const;
75
76   // getMachineOpValue - Return binary encoding of operand. If the machin
77   // operand requires relocation, record the relocation and return zero.
78  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
79                             SmallVectorImpl<MCFixup> &Fixups) const;
80
81  unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
82                          SmallVectorImpl<MCFixup> &Fixups) const;
83  unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
84                              SmallVectorImpl<MCFixup> &Fixups) const;
85  unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
86                              SmallVectorImpl<MCFixup> &Fixups) const;
87
88}; // class MipsMCCodeEmitter
89}  // namespace
90
91MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
92                                               const MCRegisterInfo &MRI,
93                                               const MCSubtargetInfo &STI,
94                                               MCContext &Ctx)
95{
96  return new MipsMCCodeEmitter(MCII, false);
97}
98
99MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
100                                               const MCRegisterInfo &MRI,
101                                               const MCSubtargetInfo &STI,
102                                               MCContext &Ctx)
103{
104  return new MipsMCCodeEmitter(MCII, true);
105}
106
107/// EncodeInstruction - Emit the instruction.
108/// Size the instruction (currently only 4 bytes
109void MipsMCCodeEmitter::
110EncodeInstruction(const MCInst &MI, raw_ostream &OS,
111                  SmallVectorImpl<MCFixup> &Fixups) const
112{
113
114  // Non-pseudo instructions that get changed for direct object
115  // only based on operand values.
116  // If this list of instructions get much longer we will move
117  // the check to a function call. Until then, this is more efficient.
118  MCInst TmpInst = MI;
119  switch (MI.getOpcode()) {
120  // If shift amount is >= 32 it the inst needs to be lowered further
121  case Mips::DSLL:
122  case Mips::DSRL:
123  case Mips::DSRA:
124    Mips::LowerLargeShift(TmpInst);
125    break;
126    // Double extract instruction is chosen by pos and size operands
127  case Mips::DEXT:
128  case Mips::DINS:
129    Mips::LowerDextDins(TmpInst);
130  }
131
132  uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
133
134  // Check for unimplemented opcodes.
135  // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
136  // so we have to special check for them.
137  unsigned Opcode = TmpInst.getOpcode();
138  if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
139    llvm_unreachable("unimplemented opcode in EncodeInstruction()");
140
141  const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
142  uint64_t TSFlags = Desc.TSFlags;
143
144  // Pseudo instructions don't get encoded and shouldn't be here
145  // in the first place!
146  if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo)
147    llvm_unreachable("Pseudo opcode found in EncodeInstruction()");
148
149  // For now all instructions are 4 bytes
150  int Size = 4; // FIXME: Have Desc.getSize() return the correct value!
151
152  EmitInstruction(Binary, Size, OS);
153}
154
155/// getBranchTargetOpValue - Return binary encoding of the branch
156/// target operand. If the machine operand requires relocation,
157/// record the relocation and return zero.
158unsigned MipsMCCodeEmitter::
159getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
160                       SmallVectorImpl<MCFixup> &Fixups) const {
161
162  const MCOperand &MO = MI.getOperand(OpNo);
163
164  // If the destination is an immediate, we have nothing to do.
165  if (MO.isImm()) return MO.getImm();
166  assert(MO.isExpr() &&
167         "getBranchTargetOpValue expects only expressions or immediates");
168
169  const MCExpr *Expr = MO.getExpr();
170  Fixups.push_back(MCFixup::Create(0, Expr,
171                                   MCFixupKind(Mips::fixup_Mips_PC16)));
172  return 0;
173}
174
175/// getJumpTargetOpValue - Return binary encoding of the jump
176/// target operand. If the machine operand requires relocation,
177/// record the relocation and return zero.
178unsigned MipsMCCodeEmitter::
179getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
180                     SmallVectorImpl<MCFixup> &Fixups) const {
181
182  const MCOperand &MO = MI.getOperand(OpNo);
183  // If the destination is an immediate, we have nothing to do.
184  if (MO.isImm()) return MO.getImm();
185  assert(MO.isExpr() &&
186         "getJumpTargetOpValue expects only expressions or an immediate");
187
188  const MCExpr *Expr = MO.getExpr();
189  Fixups.push_back(MCFixup::Create(0, Expr,
190                                   MCFixupKind(Mips::fixup_Mips_26)));
191  return 0;
192}
193
194/// getMachineOpValue - Return binary encoding of operand. If the machine
195/// operand requires relocation, record the relocation and return zero.
196unsigned MipsMCCodeEmitter::
197getMachineOpValue(const MCInst &MI, const MCOperand &MO,
198                  SmallVectorImpl<MCFixup> &Fixups) const {
199  if (MO.isReg()) {
200    unsigned Reg = MO.getReg();
201    unsigned RegNo = getMipsRegisterNumbering(Reg);
202    return RegNo;
203  } else if (MO.isImm()) {
204    return static_cast<unsigned>(MO.getImm());
205  } else if (MO.isFPImm()) {
206    return static_cast<unsigned>(APFloat(MO.getFPImm())
207        .bitcastToAPInt().getHiBits(32).getLimitedValue());
208  }
209
210  // MO must be an Expr.
211  assert(MO.isExpr());
212
213  const MCExpr *Expr = MO.getExpr();
214  MCExpr::ExprKind Kind = Expr->getKind();
215
216  if (Kind == MCExpr::Binary) {
217    Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();
218    Kind = Expr->getKind();
219  }
220
221  assert (Kind == MCExpr::SymbolRef);
222
223  Mips::Fixups FixupKind = Mips::Fixups(0);
224
225  switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
226  default: llvm_unreachable("Unknown fixup kind!");
227    break;
228  case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
229    FixupKind = Mips::fixup_Mips_GPOFF_HI;
230    break;
231  case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
232    FixupKind = Mips::fixup_Mips_GPOFF_LO;
233    break;
234  case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
235    FixupKind = Mips::fixup_Mips_GOT_PAGE;
236    break;
237  case MCSymbolRefExpr::VK_Mips_GOT_OFST :
238    FixupKind = Mips::fixup_Mips_GOT_OFST;
239    break;
240  case MCSymbolRefExpr::VK_Mips_GOT_DISP :
241    FixupKind = Mips::fixup_Mips_GOT_DISP;
242    break;
243  case MCSymbolRefExpr::VK_Mips_GPREL:
244    FixupKind = Mips::fixup_Mips_GPREL16;
245    break;
246  case MCSymbolRefExpr::VK_Mips_GOT_CALL:
247    FixupKind = Mips::fixup_Mips_CALL16;
248    break;
249  case MCSymbolRefExpr::VK_Mips_GOT16:
250    FixupKind = Mips::fixup_Mips_GOT_Global;
251    break;
252  case MCSymbolRefExpr::VK_Mips_GOT:
253    FixupKind = Mips::fixup_Mips_GOT_Local;
254    break;
255  case MCSymbolRefExpr::VK_Mips_ABS_HI:
256    FixupKind = Mips::fixup_Mips_HI16;
257    break;
258  case MCSymbolRefExpr::VK_Mips_ABS_LO:
259    FixupKind = Mips::fixup_Mips_LO16;
260    break;
261  case MCSymbolRefExpr::VK_Mips_TLSGD:
262    FixupKind = Mips::fixup_Mips_TLSGD;
263    break;
264  case MCSymbolRefExpr::VK_Mips_TLSLDM:
265    FixupKind = Mips::fixup_Mips_TLSLDM;
266    break;
267  case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
268    FixupKind = Mips::fixup_Mips_DTPREL_HI;
269    break;
270  case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
271    FixupKind = Mips::fixup_Mips_DTPREL_LO;
272    break;
273  case MCSymbolRefExpr::VK_Mips_GOTTPREL:
274    FixupKind = Mips::fixup_Mips_GOTTPREL;
275    break;
276  case MCSymbolRefExpr::VK_Mips_TPREL_HI:
277    FixupKind = Mips::fixup_Mips_TPREL_HI;
278    break;
279  case MCSymbolRefExpr::VK_Mips_TPREL_LO:
280    FixupKind = Mips::fixup_Mips_TPREL_LO;
281    break;
282  case MCSymbolRefExpr::VK_Mips_HIGHER:
283    FixupKind = Mips::fixup_Mips_HIGHER;
284    break;
285  case MCSymbolRefExpr::VK_Mips_HIGHEST:
286    FixupKind = Mips::fixup_Mips_HIGHEST;
287    break;
288  } // switch
289
290  Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind)));
291
292  // All of the information is in the fixup.
293  return 0;
294}
295
296/// getMemEncoding - Return binary encoding of memory related operand.
297/// If the offset operand requires relocation, record the relocation.
298unsigned
299MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
300                                  SmallVectorImpl<MCFixup> &Fixups) const {
301  // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
302  assert(MI.getOperand(OpNo).isReg());
303  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
304  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
305
306  return (OffBits & 0xFFFF) | RegBits;
307}
308
309unsigned
310MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
311                                      SmallVectorImpl<MCFixup> &Fixups) const {
312  assert(MI.getOperand(OpNo).isImm());
313  unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
314  return SizeEncoding - 1;
315}
316
317// FIXME: should be called getMSBEncoding
318//
319unsigned
320MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
321                                      SmallVectorImpl<MCFixup> &Fixups) const {
322  assert(MI.getOperand(OpNo-1).isImm());
323  assert(MI.getOperand(OpNo).isImm());
324  unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
325  unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
326
327  return Position + Size - 1;
328}
329
330#include "MipsGenMCCodeEmitter.inc"
331
332