MipsMCCodeEmitter.cpp revision ad51a4a5984a365d671ddfe9eaa23d2e12ee4281 
1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MipsMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13//
14#define DEBUG_TYPE "mccodeemitter"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "MCTargetDesc/MipsFixupKinds.h"
17#include "MCTargetDesc/MipsMCTargetDesc.h"
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/MC/MCCodeEmitter.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30namespace {
31class MipsMCCodeEmitter : public MCCodeEmitter {
32  MipsMCCodeEmitter(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
33  void operator=(const MipsMCCodeEmitter &); // DO NOT IMPLEMENT
34  const MCInstrInfo &MCII;
35  const MCSubtargetInfo &STI;
36  MCContext &Ctx;
37  bool IsLittleEndian;
38
39public:
40  MipsMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
41                    MCContext &ctx, bool IsLittle) :
42            MCII(mcii), STI(sti) , Ctx(ctx), IsLittleEndian(IsLittle) {}
43
44  ~MipsMCCodeEmitter() {}
45
46  void EmitByte(unsigned char C, raw_ostream &OS) const {
47    OS << (char)C;
48  }
49
50  void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
51    // Output the instruction encoding in little endian byte order.
52    for (unsigned i = 0; i < Size; ++i) {
53      unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
54      EmitByte((Val >> Shift) & 0xff, OS);
55    }
56  }
57
58  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
59                         SmallVectorImpl<MCFixup> &Fixups) const;
60
61  // getBinaryCodeForInstr - TableGen'erated function for getting the
62  // binary encoding for an instruction.
63  uint64_t getBinaryCodeForInstr(const MCInst &MI,
64                                 SmallVectorImpl<MCFixup> &Fixups) const;
65
66  // getBranchJumpOpValue - Return binary encoding of the jump
67  // target operand. If the machine operand requires relocation,
68  // record the relocation and return zero.
69   unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
70                                 SmallVectorImpl<MCFixup> &Fixups) const;
71
72   // getBranchTargetOpValue - Return binary encoding of the branch
73   // target operand. If the machine operand requires relocation,
74   // record the relocation and return zero.
75  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
76                                  SmallVectorImpl<MCFixup> &Fixups) const;
77
78   // getMachineOpValue - Return binary encoding of operand. If the machin
79   // operand requires relocation, record the relocation and return zero.
80  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
81                             SmallVectorImpl<MCFixup> &Fixups) const;
82
83  unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
84                          SmallVectorImpl<MCFixup> &Fixups) const;
85  unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
86                              SmallVectorImpl<MCFixup> &Fixups) const;
87  unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
88                              SmallVectorImpl<MCFixup> &Fixups) const;
89
90}; // class MipsMCCodeEmitter
91}  // namespace
92
93MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
94                                               const MCRegisterInfo &MRI,
95                                               const MCSubtargetInfo &STI,
96                                               MCContext &Ctx)
97{
98  return new MipsMCCodeEmitter(MCII, STI, Ctx, false);
99}
100
101MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
102                                               const MCRegisterInfo &MRI,
103                                               const MCSubtargetInfo &STI,
104                                               MCContext &Ctx)
105{
106  return new MipsMCCodeEmitter(MCII, STI, Ctx, true);
107}
108
109/// EncodeInstruction - Emit the instruction.
110/// Size the instruction (currently only 4 bytes
111void MipsMCCodeEmitter::
112EncodeInstruction(const MCInst &MI, raw_ostream &OS,
113                  SmallVectorImpl<MCFixup> &Fixups) const
114{
115  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
116
117  // Check for unimplemented opcodes.
118  // Unfortunately in MIPS both NOT and SLL will come in with Binary == 0
119  // so we have to special check for them.
120  unsigned Opcode = MI.getOpcode();
121  if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
122    llvm_unreachable("unimplemented opcode in EncodeInstruction()");
123
124  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
125  uint64_t TSFlags = Desc.TSFlags;
126
127  // Pseudo instructions don't get encoded and shouldn't be here
128  // in the first place!
129  if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo)
130    llvm_unreachable("Pseudo opcode found in EncodeInstruction()");
131
132  // For now all instructions are 4 bytes
133  int Size = 4; // FIXME: Have Desc.getSize() return the correct value!
134
135  EmitInstruction(Binary, Size, OS);
136}
137
138/// getBranchTargetOpValue - Return binary encoding of the branch
139/// target operand. If the machine operand requires relocation,
140/// record the relocation and return zero.
141unsigned MipsMCCodeEmitter::
142getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
143                       SmallVectorImpl<MCFixup> &Fixups) const {
144
145  const MCOperand &MO = MI.getOperand(OpNo);
146
147  // If the destination is an immediate, we have nothing to do.
148  if (MO.isImm()) return MO.getImm();
149  assert(MO.isExpr() &&
150         "getBranchTargetOpValue expects only expressions or immediates");
151
152  const MCExpr *Expr = MO.getExpr();
153  Fixups.push_back(MCFixup::Create(0, Expr,
154                                   MCFixupKind(Mips::fixup_Mips_PC16)));
155  return 0;
156}
157
158/// getJumpTargetOpValue - Return binary encoding of the jump
159/// target operand. If the machine operand requires relocation,
160/// record the relocation and return zero.
161unsigned MipsMCCodeEmitter::
162getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
163                     SmallVectorImpl<MCFixup> &Fixups) const {
164
165  const MCOperand &MO = MI.getOperand(OpNo);
166  // If the destination is an immediate, we have nothing to do.
167  if (MO.isImm()) return MO.getImm();
168  assert(MO.isExpr() &&
169         "getJumpTargetOpValue expects only expressions or an immediate");
170
171  const MCExpr *Expr = MO.getExpr();
172  Fixups.push_back(MCFixup::Create(0, Expr,
173                                   MCFixupKind(Mips::fixup_Mips_26)));
174  return 0;
175}
176
177/// getMachineOpValue - Return binary encoding of operand. If the machine
178/// operand requires relocation, record the relocation and return zero.
179unsigned MipsMCCodeEmitter::
180getMachineOpValue(const MCInst &MI, const MCOperand &MO,
181                  SmallVectorImpl<MCFixup> &Fixups) const {
182  if (MO.isReg()) {
183    unsigned Reg = MO.getReg();
184    unsigned RegNo = getMipsRegisterNumbering(Reg);
185    return RegNo;
186  } else if (MO.isImm()) {
187    return static_cast<unsigned>(MO.getImm());
188  } else if (MO.isFPImm()) {
189    return static_cast<unsigned>(APFloat(MO.getFPImm())
190        .bitcastToAPInt().getHiBits(32).getLimitedValue());
191  }
192
193  // MO must be an Expr.
194  assert(MO.isExpr());
195
196  const MCExpr *Expr = MO.getExpr();
197  MCExpr::ExprKind Kind = Expr->getKind();
198
199  if (Kind == MCExpr::Binary) {
200    Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();
201    Kind = Expr->getKind();
202  }
203
204  assert (Kind == MCExpr::SymbolRef);
205
206  Mips::Fixups FixupKind = Mips::Fixups(0);
207
208  switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
209  default: llvm_unreachable("Unknown fixup kind!");
210    break;
211  case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
212    FixupKind = Mips::fixup_Mips_GPOFF_HI;
213    break;
214  case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
215    FixupKind = Mips::fixup_Mips_GPOFF_LO;
216    break;
217  case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
218    FixupKind = Mips::fixup_Mips_GOT_PAGE;
219    break;
220  case MCSymbolRefExpr::VK_Mips_GOT_OFST :
221    FixupKind = Mips::fixup_Mips_GOT_OFST;
222    break;
223  case MCSymbolRefExpr::VK_Mips_GOT_DISP :
224    FixupKind = Mips::fixup_Mips_GOT_DISP;
225    break;
226  case MCSymbolRefExpr::VK_Mips_GPREL:
227    FixupKind = Mips::fixup_Mips_GPREL16;
228    break;
229  case MCSymbolRefExpr::VK_Mips_GOT_CALL:
230    FixupKind = Mips::fixup_Mips_CALL16;
231    break;
232  case MCSymbolRefExpr::VK_Mips_GOT16:
233    FixupKind = Mips::fixup_Mips_GOT_Global;
234    break;
235  case MCSymbolRefExpr::VK_Mips_GOT:
236    FixupKind = Mips::fixup_Mips_GOT_Local;
237    break;
238  case MCSymbolRefExpr::VK_Mips_ABS_HI:
239    FixupKind = Mips::fixup_Mips_HI16;
240    break;
241  case MCSymbolRefExpr::VK_Mips_ABS_LO:
242    FixupKind = Mips::fixup_Mips_LO16;
243    break;
244  case MCSymbolRefExpr::VK_Mips_TLSGD:
245    FixupKind = Mips::fixup_Mips_TLSGD;
246    break;
247  case MCSymbolRefExpr::VK_Mips_TLSLDM:
248    FixupKind = Mips::fixup_Mips_TLSLDM;
249    break;
250  case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
251    FixupKind = Mips::fixup_Mips_DTPREL_HI;
252    break;
253  case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
254    FixupKind = Mips::fixup_Mips_DTPREL_LO;
255    break;
256  case MCSymbolRefExpr::VK_Mips_GOTTPREL:
257    FixupKind = Mips::fixup_Mips_GOTTPREL;
258    break;
259  case MCSymbolRefExpr::VK_Mips_TPREL_HI:
260    FixupKind = Mips::fixup_Mips_TPREL_HI;
261    break;
262  case MCSymbolRefExpr::VK_Mips_TPREL_LO:
263    FixupKind = Mips::fixup_Mips_TPREL_LO;
264    break;
265  case MCSymbolRefExpr::VK_Mips_HIGHER:
266    FixupKind = Mips::fixup_Mips_HIGHER;
267    break;
268  case MCSymbolRefExpr::VK_Mips_HIGHEST:
269    FixupKind = Mips::fixup_Mips_HIGHEST;
270    break;
271  } // switch
272
273  Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind)));
274
275  // All of the information is in the fixup.
276  return 0;
277}
278
279/// getMemEncoding - Return binary encoding of memory related operand.
280/// If the offset operand requires relocation, record the relocation.
281unsigned
282MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
283                                  SmallVectorImpl<MCFixup> &Fixups) const {
284  // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
285  assert(MI.getOperand(OpNo).isReg());
286  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
287  unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
288
289  return (OffBits & 0xFFFF) | RegBits;
290}
291
292unsigned
293MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
294                                      SmallVectorImpl<MCFixup> &Fixups) const {
295  assert(MI.getOperand(OpNo).isImm());
296  unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
297  return SizeEncoding - 1;
298}
299
300// FIXME: should be called getMSBEncoding
301//
302unsigned
303MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
304                                      SmallVectorImpl<MCFixup> &Fixups) const {
305  assert(MI.getOperand(OpNo-1).isImm());
306  assert(MI.getOperand(OpNo).isImm());
307  unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
308  unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
309
310  return Position + Size - 1;
311}
312
313#include "MipsGenMCCodeEmitter.inc"
314
315