MipsMCCodeEmitter.cpp revision d3107fbc54a5b5156f0aabc8788724f1469eb9df
1//===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the MipsMCCodeEmitter class. 11// 12//===----------------------------------------------------------------------===// 13// 14#define DEBUG_TYPE "mccodeemitter" 15#include "MCTargetDesc/MipsBaseInfo.h" 16#include "MCTargetDesc/MipsDirectObjLower.h" 17#include "MCTargetDesc/MipsFixupKinds.h" 18#include "MCTargetDesc/MipsMCTargetDesc.h" 19#include "llvm/ADT/APFloat.h" 20#include "llvm/ADT/Statistic.h" 21#include "llvm/MC/MCCodeEmitter.h" 22#include "llvm/MC/MCContext.h" 23#include "llvm/MC/MCExpr.h" 24#include "llvm/MC/MCInst.h" 25#include "llvm/MC/MCInstrInfo.h" 26#include "llvm/MC/MCRegisterInfo.h" 27#include "llvm/MC/MCSubtargetInfo.h" 28#include "llvm/Support/raw_ostream.h" 29 30using namespace llvm; 31 32namespace { 33class MipsMCCodeEmitter : public MCCodeEmitter { 34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION; 35 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION; 36 const MCInstrInfo &MCII; 37 MCContext &Ctx; 38 bool IsLittleEndian; 39 40public: 41 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, 42 const MCSubtargetInfo &sti, bool IsLittle) : 43 MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} 44 45 ~MipsMCCodeEmitter() {} 46 47 void EmitByte(unsigned char C, raw_ostream &OS) const { 48 OS << (char)C; 49 } 50 51 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const { 52 // Output the instruction encoding in little endian byte order. 53 for (unsigned i = 0; i < Size; ++i) { 54 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; 55 EmitByte((Val >> Shift) & 0xff, OS); 56 } 57 } 58 59 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 60 SmallVectorImpl<MCFixup> &Fixups) const; 61 62 // getBinaryCodeForInstr - TableGen'erated function for getting the 63 // binary encoding for an instruction. 64 uint64_t getBinaryCodeForInstr(const MCInst &MI, 65 SmallVectorImpl<MCFixup> &Fixups) const; 66 67 // getBranchJumpOpValue - Return binary encoding of the jump 68 // target operand. If the machine operand requires relocation, 69 // record the relocation and return zero. 70 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 71 SmallVectorImpl<MCFixup> &Fixups) const; 72 73 // getBranchTargetOpValue - Return binary encoding of the branch 74 // target operand. If the machine operand requires relocation, 75 // record the relocation and return zero. 76 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 77 SmallVectorImpl<MCFixup> &Fixups) const; 78 79 // getMachineOpValue - Return binary encoding of operand. If the machin 80 // operand requires relocation, record the relocation and return zero. 81 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 82 SmallVectorImpl<MCFixup> &Fixups) const; 83 84 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, 85 SmallVectorImpl<MCFixup> &Fixups) const; 86 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, 87 SmallVectorImpl<MCFixup> &Fixups) const; 88 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 89 SmallVectorImpl<MCFixup> &Fixups) const; 90 91}; // class MipsMCCodeEmitter 92} // namespace 93 94MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 95 const MCRegisterInfo &MRI, 96 const MCSubtargetInfo &STI, 97 MCContext &Ctx) 98{ 99 return new MipsMCCodeEmitter(MCII, Ctx, STI, false); 100} 101 102MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, 103 const MCRegisterInfo &MRI, 104 const MCSubtargetInfo &STI, 105 MCContext &Ctx) 106{ 107 return new MipsMCCodeEmitter(MCII, Ctx, STI, true); 108} 109 110/// EncodeInstruction - Emit the instruction. 111/// Size the instruction (currently only 4 bytes 112void MipsMCCodeEmitter:: 113EncodeInstruction(const MCInst &MI, raw_ostream &OS, 114 SmallVectorImpl<MCFixup> &Fixups) const 115{ 116 117 // Non-pseudo instructions that get changed for direct object 118 // only based on operand values. 119 // If this list of instructions get much longer we will move 120 // the check to a function call. Until then, this is more efficient. 121 MCInst TmpInst = MI; 122 switch (MI.getOpcode()) { 123 // If shift amount is >= 32 it the inst needs to be lowered further 124 case Mips::DSLL: 125 case Mips::DSRL: 126 case Mips::DSRA: 127 Mips::LowerLargeShift(TmpInst); 128 break; 129 // Double extract instruction is chosen by pos and size operands 130 case Mips::DEXT: 131 case Mips::DINS: 132 Mips::LowerDextDins(TmpInst); 133 } 134 135 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups); 136 137 // Check for unimplemented opcodes. 138 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 139 // so we have to special check for them. 140 unsigned Opcode = TmpInst.getOpcode(); 141 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary) 142 llvm_unreachable("unimplemented opcode in EncodeInstruction()"); 143 144 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); 145 146 // Get byte count of instruction 147 unsigned Size = Desc.getSize(); 148 if (!Size) 149 llvm_unreachable("Desc.getSize() returns 0"); 150 151 EmitInstruction(Binary, Size, OS); 152} 153 154/// getBranchTargetOpValue - Return binary encoding of the branch 155/// target operand. If the machine operand requires relocation, 156/// record the relocation and return zero. 157unsigned MipsMCCodeEmitter:: 158getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 159 SmallVectorImpl<MCFixup> &Fixups) const { 160 161 const MCOperand &MO = MI.getOperand(OpNo); 162 163 // If the destination is an immediate, divide by 4. 164 if (MO.isImm()) return MO.getImm() >> 2; 165 166 assert(MO.isExpr() && 167 "getBranchTargetOpValue expects only expressions or immediates"); 168 169 const MCExpr *Expr = MO.getExpr(); 170 Fixups.push_back(MCFixup::Create(0, Expr, 171 MCFixupKind(Mips::fixup_Mips_PC16))); 172 return 0; 173} 174 175/// getJumpTargetOpValue - Return binary encoding of the jump 176/// target operand. If the machine operand requires relocation, 177/// record the relocation and return zero. 178unsigned MipsMCCodeEmitter:: 179getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, 180 SmallVectorImpl<MCFixup> &Fixups) const { 181 182 const MCOperand &MO = MI.getOperand(OpNo); 183 // If the destination is an immediate, divide by 4. 184 if (MO.isImm()) return MO.getImm()>>2; 185 186 assert(MO.isExpr() && 187 "getJumpTargetOpValue expects only expressions or an immediate"); 188 189 const MCExpr *Expr = MO.getExpr(); 190 Fixups.push_back(MCFixup::Create(0, Expr, 191 MCFixupKind(Mips::fixup_Mips_26))); 192 return 0; 193} 194 195/// getMachineOpValue - Return binary encoding of operand. If the machine 196/// operand requires relocation, record the relocation and return zero. 197unsigned MipsMCCodeEmitter:: 198getMachineOpValue(const MCInst &MI, const MCOperand &MO, 199 SmallVectorImpl<MCFixup> &Fixups) const { 200 if (MO.isReg()) { 201 unsigned Reg = MO.getReg(); 202 unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg); 203 return RegNo; 204 } else if (MO.isImm()) { 205 return static_cast<unsigned>(MO.getImm()); 206 } else if (MO.isFPImm()) { 207 return static_cast<unsigned>(APFloat(MO.getFPImm()) 208 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 209 } 210 211 // MO must be an Expr. 212 assert(MO.isExpr()); 213 214 const MCExpr *Expr = MO.getExpr(); 215 MCExpr::ExprKind Kind = Expr->getKind(); 216 217 if (Kind == MCExpr::Binary) { 218 Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS(); 219 Kind = Expr->getKind(); 220 } 221 222 assert (Kind == MCExpr::SymbolRef); 223 224 Mips::Fixups FixupKind = Mips::Fixups(0); 225 226 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { 227 default: llvm_unreachable("Unknown fixup kind!"); 228 break; 229 case MCSymbolRefExpr::VK_Mips_GPOFF_HI : 230 FixupKind = Mips::fixup_Mips_GPOFF_HI; 231 break; 232 case MCSymbolRefExpr::VK_Mips_GPOFF_LO : 233 FixupKind = Mips::fixup_Mips_GPOFF_LO; 234 break; 235 case MCSymbolRefExpr::VK_Mips_GOT_PAGE : 236 FixupKind = Mips::fixup_Mips_GOT_PAGE; 237 break; 238 case MCSymbolRefExpr::VK_Mips_GOT_OFST : 239 FixupKind = Mips::fixup_Mips_GOT_OFST; 240 break; 241 case MCSymbolRefExpr::VK_Mips_GOT_DISP : 242 FixupKind = Mips::fixup_Mips_GOT_DISP; 243 break; 244 case MCSymbolRefExpr::VK_Mips_GPREL: 245 FixupKind = Mips::fixup_Mips_GPREL16; 246 break; 247 case MCSymbolRefExpr::VK_Mips_GOT_CALL: 248 FixupKind = Mips::fixup_Mips_CALL16; 249 break; 250 case MCSymbolRefExpr::VK_Mips_GOT16: 251 FixupKind = Mips::fixup_Mips_GOT_Global; 252 break; 253 case MCSymbolRefExpr::VK_Mips_GOT: 254 FixupKind = Mips::fixup_Mips_GOT_Local; 255 break; 256 case MCSymbolRefExpr::VK_Mips_ABS_HI: 257 FixupKind = Mips::fixup_Mips_HI16; 258 break; 259 case MCSymbolRefExpr::VK_Mips_ABS_LO: 260 FixupKind = Mips::fixup_Mips_LO16; 261 break; 262 case MCSymbolRefExpr::VK_Mips_TLSGD: 263 FixupKind = Mips::fixup_Mips_TLSGD; 264 break; 265 case MCSymbolRefExpr::VK_Mips_TLSLDM: 266 FixupKind = Mips::fixup_Mips_TLSLDM; 267 break; 268 case MCSymbolRefExpr::VK_Mips_DTPREL_HI: 269 FixupKind = Mips::fixup_Mips_DTPREL_HI; 270 break; 271 case MCSymbolRefExpr::VK_Mips_DTPREL_LO: 272 FixupKind = Mips::fixup_Mips_DTPREL_LO; 273 break; 274 case MCSymbolRefExpr::VK_Mips_GOTTPREL: 275 FixupKind = Mips::fixup_Mips_GOTTPREL; 276 break; 277 case MCSymbolRefExpr::VK_Mips_TPREL_HI: 278 FixupKind = Mips::fixup_Mips_TPREL_HI; 279 break; 280 case MCSymbolRefExpr::VK_Mips_TPREL_LO: 281 FixupKind = Mips::fixup_Mips_TPREL_LO; 282 break; 283 case MCSymbolRefExpr::VK_Mips_HIGHER: 284 FixupKind = Mips::fixup_Mips_HIGHER; 285 break; 286 case MCSymbolRefExpr::VK_Mips_HIGHEST: 287 FixupKind = Mips::fixup_Mips_HIGHEST; 288 break; 289 case MCSymbolRefExpr::VK_Mips_GOT_HI16: 290 FixupKind = Mips::fixup_Mips_GOT_HI16; 291 break; 292 case MCSymbolRefExpr::VK_Mips_GOT_LO16: 293 FixupKind = Mips::fixup_Mips_GOT_LO16; 294 break; 295 case MCSymbolRefExpr::VK_Mips_CALL_HI16: 296 FixupKind = Mips::fixup_Mips_CALL_HI16; 297 break; 298 case MCSymbolRefExpr::VK_Mips_CALL_LO16: 299 FixupKind = Mips::fixup_Mips_CALL_LO16; 300 break; 301 } // switch 302 303 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind))); 304 305 // All of the information is in the fixup. 306 return 0; 307} 308 309/// getMemEncoding - Return binary encoding of memory related operand. 310/// If the offset operand requires relocation, record the relocation. 311unsigned 312MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, 313 SmallVectorImpl<MCFixup> &Fixups) const { 314 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. 315 assert(MI.getOperand(OpNo).isReg()); 316 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; 317 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); 318 319 return (OffBits & 0xFFFF) | RegBits; 320} 321 322unsigned 323MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, 324 SmallVectorImpl<MCFixup> &Fixups) const { 325 assert(MI.getOperand(OpNo).isImm()); 326 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); 327 return SizeEncoding - 1; 328} 329 330// FIXME: should be called getMSBEncoding 331// 332unsigned 333MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, 334 SmallVectorImpl<MCFixup> &Fixups) const { 335 assert(MI.getOperand(OpNo-1).isImm()); 336 assert(MI.getOperand(OpNo).isImm()); 337 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups); 338 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); 339 340 return Position + Size - 1; 341} 342 343#include "MipsGenMCCodeEmitter.inc" 344 345