MipsMCTargetDesc.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides Mips specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSMCTARGETDESC_H
15#define MIPSMCTARGETDESC_H
16
17#include "llvm/Support/DataTypes.h"
18
19namespace llvm {
20class MCAsmBackend;
21class MCCodeEmitter;
22class MCContext;
23class MCInstrInfo;
24class MCObjectWriter;
25class MCRegisterInfo;
26class MCSubtargetInfo;
27class StringRef;
28class Target;
29class raw_ostream;
30
31extern Target TheMipsTarget;
32extern Target TheMipselTarget;
33extern Target TheMips64Target;
34extern Target TheMips64elTarget;
35
36MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37                                         const MCRegisterInfo &MRI,
38                                         const MCSubtargetInfo &STI,
39                                         MCContext &Ctx);
40MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
41                                         const MCRegisterInfo &MRI,
42                                         const MCSubtargetInfo &STI,
43                                         MCContext &Ctx);
44
45MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
46                                       const MCRegisterInfo &MRI, StringRef TT,
47                                       StringRef CPU);
48MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
49                                       const MCRegisterInfo &MRI, StringRef TT,
50                                       StringRef CPU);
51MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
52                                       const MCRegisterInfo &MRI, StringRef TT,
53                                       StringRef CPU);
54MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
55                                       const MCRegisterInfo &MRI, StringRef TT,
56                                       StringRef CPU);
57
58MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS,
59                                          uint8_t OSABI,
60                                          bool IsLittleEndian,
61                                          bool Is64Bit);
62} // End llvm namespace
63
64// Defines symbolic names for Mips registers.  This defines a mapping from
65// register name to register number.
66#define GET_REGINFO_ENUM
67#include "MipsGenRegisterInfo.inc"
68
69// Defines symbolic names for the Mips instructions.
70#define GET_INSTRINFO_ENUM
71#include "MipsGenInstrInfo.inc"
72
73#define GET_SUBTARGETINFO_ENUM
74#include "MipsGenSubtargetInfo.inc"
75
76#endif
77