MipsMCTargetDesc.h revision c3cee57f7d20f69a84fd88464ed8cf050e63c7ad 
1//===-- MipsMCTargetDesc.h - Mips Target Descriptions -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides Mips specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSMCTARGETDESC_H
15#define MIPSMCTARGETDESC_H
16
17#include "llvm/Support/DataTypes.h"
18
19namespace llvm {
20class MCAsmBackend;
21class MCCodeEmitter;
22class MCContext;
23class MCInstrInfo;
24class MCObjectWriter;
25class MCRegisterInfo;
26class MCSubtargetInfo;
27class StringRef;
28class Target;
29class raw_ostream;
30
31extern Target TheMipsTarget;
32extern Target TheMipselTarget;
33extern Target TheMips64Target;
34extern Target TheMips64elTarget;
35
36MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
37                                         const MCRegisterInfo &MRI,
38                                         const MCSubtargetInfo &STI,
39                                         MCContext &Ctx);
40MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
41                                         const MCRegisterInfo &MRI,
42                                         const MCSubtargetInfo &STI,
43                                         MCContext &Ctx);
44
45MCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI,
46                                       StringRef TT, StringRef CPU);
47MCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI,
48                                       StringRef TT, StringRef CPU);
49MCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI,
50                                       StringRef TT, StringRef CPU);
51MCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI,
52                                       StringRef TT, StringRef CPU);
53
54MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS,
55                                          uint8_t OSABI,
56                                          bool IsLittleEndian,
57                                          bool Is64Bit);
58} // End llvm namespace
59
60// Defines symbolic names for Mips registers.  This defines a mapping from
61// register name to register number.
62#define GET_REGINFO_ENUM
63#include "MipsGenRegisterInfo.inc"
64
65// Defines symbolic names for the Mips instructions.
66#define GET_INSTRINFO_ENUM
67#include "MipsGenInstrInfo.inc"
68
69#define GET_SUBTARGETINFO_ENUM
70#include "MipsGenSubtargetInfo.inc"
71
72#endif
73