MSA.txt revision c385709d8397ca1535481c04564b67d07c66c619 
1Code Generation Notes for MSA
2=============================
3
4Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
5optimisation, reduce the size of the ISel matcher, and reduce repetition in
6the implementation. In a small number of cases, this can cause different
7(semantically equivalent) instructions to be used in place of the requested
8instruction, even when no optimisation has taken place.
9
10Instructions
11============
12
13This section describes any quirks of instruction selection for MSA. For
14example, two instructions might be equally valid for some given IR and one is
15chosen in preference to the other.
16
17vshf.w:
18        It is not possible to emit vshf.w when the shuffle description is
19        constant since shf.w covers exactly the same cases. shf.w is used
20        instead. It is also impossible for the shuffle description to be
21        unknown at compile-time due to the definition of shufflevector in
22        LLVM IR.
23
24vshf.[bhwd]
25        When the shuffle description describes a splat operation, splat.[bhwd]
26        instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*,
27        and pck* instructions, this is matched from MipsISD::VSHF instead of
28        a special-case MipsISD node.
29
30ilvl.d, pckev.d:
31        It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
32        same shuffle. ilvev.d will be emitted instead.
33
34ilvr.d, ilvod.d, pckod.d:
35        It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the
36        same shuffle. ilvod.d will be emitted instead.
37
38splat.[bhwd]
39        The intrinsic will work as expected. However, unlike other intrinsics
40        it lowers directly to MipsISD::VSHF instead of using common IR.
41
42splati.w:
43        It is not possible to emit splati.w since shf.w covers the same cases.
44        shf.w will be emitted instead.
45
46copy_s.w:
47        On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
48        copy_u.w. This is semantically equivalent since the general-purpose
49        register file is 32-bits wide.
50
51binsri.[bhwd],  binsli.[bhwd]:
52        These two operations are equivalent to each other with the operands
53        swapped and condition inverted. The compiler may use either one as
54        appropriate.
55        Furthermore, the compiler may use bsel.[bhwd] for some masks that do
56        not survive the legalization process (this is a bug and will be fixed).
57
58bmnz.v, bmz.v, bsel.v:
59        These three operations differ only in the operand that is tied to the
60        result.
61        It is (currently) not possible to emit bmz.v, or bsel.v since bmnz.v is
62        the same operation and will be emitted instead.
63        In future, the compiler may choose between these three instructions
64        according to register allocation.
65
66bmnzi.b, bmzi.b:
67        Like their non-immediate counterparts, bmnzi.v and bmzi.v are the same
68        operation with the operands swapped. bmnzi.v will (currently) be emitted
69        for both cases.
70
71bseli.v:
72        Unlike the non-immediate versions, bseli.v is distinguishable from
73        bmnzi.b and bmzi.b and can be emitted.
74