MSA.txt revision e8eafdb67685d4f5d52ab0dce2339c37e39cdc44 
1Code Generation Notes for MSA
2=============================
3
4Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
5optimisation, reduce the size of the ISel matcher, and reduce repetition in
6the implementation. In a small number of cases, this can cause different
7(semantically equivalent) instructions to be used in place of the requested
8instruction, even when no optimisation has taken place.
9
10Instructions
11============
12
13This section describes any quirks of instruction selection for MSA. For
14example, two instructions might be equally valid for some given IR and one is
15chosen in preference to the other.
16
17vshf.w:
18        It is not possible to emit vshf.w when the shuffle description is
19        constant since shf.w covers exactly the same cases. shf.w is used
20        instead. It is also impossible for the shuffle description to be
21        unknown at compile-time due to the definition of shufflevector in
22        LLVM IR.
23
24ilvl.d, pckev.d:
25        It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
26        same shuffle. ilvev.d will be emitted instead.
27
28ilvr.d, ilvod.d, pckod.d:
29        It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the
30        same shuffle. ilvod.d will be emitted instead.
31
32splati.w:
33        It is not possible to emit splati.w since shf.w covers the same cases.
34        shf.w will be emitted instead.
35
36copy_s.w
37        On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
38        copy_u.w. This is semantically equivalent since the general-purpose
39        register file is 32-bits wide.
40