MicroMipsInstrInfo.td revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2
3def simm12 : Operand<i32> {
4  let DecoderMethod = "DecodeSimm12";
5}
6
7def mem_mm_12 : Operand<i32> {
8  let PrintMethod = "printMemOperand";
9  let MIOperandInfo = (ops GPR32, simm12);
10  let EncoderMethod = "getMemEncodingMMImm12";
11  let ParserMatchClass = MipsMemAsmOperand;
12  let OperandType = "OPERAND_MEMORY";
13}
14
15def jmptarget_mm : Operand<OtherVT> {
16  let EncoderMethod = "getJumpTargetOpValueMM";
17}
18
19def calltarget_mm : Operand<iPTR> {
20  let EncoderMethod = "getJumpTargetOpValueMM";
21}
22
23def brtarget_mm : Operand<OtherVT> {
24  let EncoderMethod = "getBranchTargetOpValueMM";
25  let OperandType   = "OPERAND_PCREL";
26  let DecoderMethod = "DecodeBranchTargetMM";
27}
28
29let canFoldAsLoad = 1 in
30class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
31                      Operand MemOpnd> :
32  InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
33         !strconcat(opstr, "\t$rt, $addr"),
34         [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
35         NoItinerary, FrmI> {
36  let DecoderMethod = "DecodeMemMMImm12";
37  string Constraints = "$src = $rt";
38}
39
40class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
41                       Operand MemOpnd>:
42  InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
43         !strconcat(opstr, "\t$rt, $addr"),
44         [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
45  let DecoderMethod = "DecodeMemMMImm12";
46}
47
48class LLBaseMM<string opstr, RegisterOperand RO> :
49  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
50         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
51  let DecoderMethod = "DecodeMemMMImm12";
52  let mayLoad = 1;
53}
54
55class SCBaseMM<string opstr, RegisterOperand RO> :
56  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
57         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
58  let DecoderMethod = "DecodeMemMMImm12";
59  let mayStore = 1;
60  let Constraints = "$rt = $dst";
61}
62
63class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
64             InstrItinClass Itin = NoItinerary> :
65  InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
66         !strconcat(opstr, "\t$rt, $addr"),
67         [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
68  let DecoderMethod = "DecodeMemMMImm12";
69  let canFoldAsLoad = 1;
70  let mayLoad = 1;
71}
72
73class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
74      MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
75  [], II_MFHI_MFLO, FrmR> {
76  let Uses = [UseReg];
77  let hasSideEffects = 0;
78}
79
80class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
81               InstrItinClass Itin = NoItinerary> :
82  MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
83                  !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> {
84  let isCommutable = isComm;
85  let isReMaterializable = 1;
86}
87
88// 16-bit Jump and Link (Call)
89class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
90  MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
91           [(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
92  let isCall = 1;
93  let hasDelaySlot = 1;
94  let Defs = [RA];
95}
96
97def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
98def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
99def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
100def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>;
101
102class WaitMM<string opstr> :
103  InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
104         NoItinerary, FrmOther, opstr>;
105
106let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
107  /// Arithmetic Instructions (ALU Immediate)
108  def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
109                 ADDI_FM_MM<0xc>;
110  def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
111                 ADDI_FM_MM<0x4>;
112  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
113                 SLTI_FM_MM<0x24>;
114  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
115                 SLTI_FM_MM<0x2c>;
116  def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
117                 ADDI_FM_MM<0x34>;
118  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
119                 ADDI_FM_MM<0x14>;
120  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
121                 ADDI_FM_MM<0x1c>;
122  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
123
124  def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
125                     LW_FM_MM<0xc>;
126
127  /// Arithmetic Instructions (3-Operand, R-Type)
128  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
129  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
130  def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
131  def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
132  def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
133  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
134  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
135                 ADD_FM_MM<0, 0x390>;
136  def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
137                 ADD_FM_MM<0, 0x250>;
138  def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
139                 ADD_FM_MM<0, 0x290>;
140  def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
141                 ADD_FM_MM<0, 0x310>;
142  def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
143  def MULT_MM  : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
144                 MULT_FM_MM<0x22c>;
145  def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
146                 MULT_FM_MM<0x26c>;
147  def SDIV_MM  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
148                 MULT_FM_MM<0x2ac>;
149  def UDIV_MM  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
150                 MULT_FM_MM<0x2ec>;
151
152  /// Shift Instructions
153  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
154                 SRA_FM_MM<0, 0>;
155  def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
156                 SRA_FM_MM<0x40, 0>;
157  def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
158                 SRA_FM_MM<0x80, 0>;
159  def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
160                 SRLV_FM_MM<0x10, 0>;
161  def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
162                 SRLV_FM_MM<0x50, 0>;
163  def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
164                 SRLV_FM_MM<0x90, 0>;
165  def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
166                 SRA_FM_MM<0xc0, 0>;
167  def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
168                 SRLV_FM_MM<0xd0, 0>;
169
170  /// Load and Store Instructions - aligned
171  let DecoderMethod = "DecodeMemMMImm16" in {
172    def LB_MM  : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
173    def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
174    def LH_MM  : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
175    def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
176    def LW_MM  : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
177    def SB_MM  : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
178    def SH_MM  : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
179    def SW_MM  : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
180  }
181
182  def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
183
184  /// Load and Store Instructions - unaligned
185  def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
186               LWL_FM_MM<0x0>;
187  def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
188               LWL_FM_MM<0x1>;
189  def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
190               LWL_FM_MM<0x8>;
191  def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
192               LWL_FM_MM<0x9>;
193
194  /// Move Conditional
195  def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
196                  NoItinerary>, ADD_FM_MM<0, 0x58>;
197  def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
198                  NoItinerary>, ADD_FM_MM<0, 0x18>;
199  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>,
200                  CMov_F_I_FM_MM<0x25>;
201  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>,
202                  CMov_F_I_FM_MM<0x5>;
203
204  /// Move to/from HI/LO
205  def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
206                MTLO_FM_MM<0x0b5>;
207  def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
208                MTLO_FM_MM<0x0f5>;
209  def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
210                MFLO_FM_MM<0x035>;
211  def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
212                MFLO_FM_MM<0x075>;
213
214  /// Multiply Add/Sub Instructions
215  def MADD_MM  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
216  def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
217  def MSUB_MM  : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
218  def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
219
220  /// Count Leading
221  def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>;
222  def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>;
223
224  /// Sign Ext In Register Instructions.
225  def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM_MM<0x0ac>;
226  def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM_MM<0x0ec>;
227
228  /// Word Swap Bytes Within Halfwords
229  def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>;
230
231  def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
232               EXT_FM_MM<0x2c>;
233  def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
234               EXT_FM_MM<0x0c>;
235
236  /// Jump Instructions
237  let DecoderMethod = "DecodeJumpTargetMM" in {
238    def J_MM        : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
239                      J_FM_MM<0x35>;
240    def JAL_MM      : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
241  }
242  def JR_MM   : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
243  def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
244  def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
245
246  /// Branch Instructions
247  def BEQ_MM  : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
248                BEQ_FM_MM<0x25>;
249  def BNE_MM  : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
250                BEQ_FM_MM<0x2d>;
251  def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
252                BGEZ_FM_MM<0x2>;
253  def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
254                BGEZ_FM_MM<0x6>;
255  def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
256                BGEZ_FM_MM<0x4>;
257  def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
258                BGEZ_FM_MM<0x0>;
259  def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
260                  BGEZAL_FM_MM<0x03>;
261  def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
262                  BGEZAL_FM_MM<0x01>;
263
264  /// Control Instructions
265  def SYNC_MM    : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
266  def BREAK_MM   : MMRel, BRK_FT<"break">, BRK_FM_MM;
267  def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM;
268  def WAIT_MM    : WaitMM<"wait">, WAIT_FM_MM;
269  def ERET_MM    : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>;
270  def DERET_MM   : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>;
271  def EI_MM      : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>;
272  def DI_MM      : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>;
273
274  /// Trap Instructions
275  def TEQ_MM  : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
276  def TGE_MM  : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
277  def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
278  def TLT_MM  : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
279  def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
280  def TNE_MM  : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
281
282  def TEQI_MM  : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>;
283  def TGEI_MM  : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>;
284  def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>;
285  def TLTI_MM  : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>;
286  def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>;
287  def TNEI_MM  : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>;
288
289  /// Load-linked, Store-conditional
290  def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
291  def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
292}
293
294//===----------------------------------------------------------------------===//
295// MicroMips instruction aliases
296//===----------------------------------------------------------------------===//
297
298let Predicates = [InMicroMips] in {
299  def : InstAlias<"wait", (WAIT_MM 0x0), 1>;
300}
301