MicroMipsInstrInfo.td revision 9f471750fa6f34120d4758d5d14f54f899e34a54 
1def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2
3def simm12 : Operand<i32> {
4  let DecoderMethod = "DecodeSimm12";
5}
6
7def mem_mm_12 : Operand<i32> {
8  let PrintMethod = "printMemOperand";
9  let MIOperandInfo = (ops GPR32, simm12);
10  let EncoderMethod = "getMemEncodingMMImm12";
11  let ParserMatchClass = MipsMemAsmOperand;
12  let OperandType = "OPERAND_MEMORY";
13}
14
15def jmptarget_mm : Operand<OtherVT> {
16  let EncoderMethod = "getJumpTargetOpValueMM";
17}
18
19def calltarget_mm : Operand<iPTR> {
20  let EncoderMethod = "getJumpTargetOpValueMM";
21}
22
23def brtarget_mm : Operand<OtherVT> {
24  let EncoderMethod = "getBranchTargetOpValueMM";
25  let OperandType   = "OPERAND_PCREL";
26  let DecoderMethod = "DecodeBranchTargetMM";
27}
28
29let canFoldAsLoad = 1 in
30class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
31                      Operand MemOpnd> :
32  InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
33         !strconcat(opstr, "\t$rt, $addr"),
34         [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
35         NoItinerary, FrmI> {
36  let DecoderMethod = "DecodeMemMMImm12";
37  string Constraints = "$src = $rt";
38}
39
40class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
41                       Operand MemOpnd>:
42  InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
43         !strconcat(opstr, "\t$rt, $addr"),
44         [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
45  let DecoderMethod = "DecodeMemMMImm12";
46}
47
48let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
49  /// Arithmetic Instructions (ALU Immediate)
50  def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
51                 ADDI_FM_MM<0xc>;
52  def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
53                 ADDI_FM_MM<0x4>;
54  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
55                 SLTI_FM_MM<0x24>;
56  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
57                 SLTI_FM_MM<0x2c>;
58  def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
59                 ADDI_FM_MM<0x34>;
60  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
61                 ADDI_FM_MM<0x14>;
62  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
63                 ADDI_FM_MM<0x1c>;
64  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
65
66  /// Arithmetic Instructions (3-Operand, R-Type)
67  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
68  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
69  def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
70  def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
71  def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
72  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
73  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
74                 ADD_FM_MM<0, 0x390>;
75  def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IIAlu, and>,
76                 ADD_FM_MM<0, 0x250>;
77  def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IIAlu, or>,
78                 ADD_FM_MM<0, 0x290>;
79  def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
80                 ADD_FM_MM<0, 0x310>;
81  def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
82  def MULT_MM  : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI0, LO0]>,
83                 MULT_FM_MM<0x22c>;
84  def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>,
85                 MULT_FM_MM<0x26c>;
86  def SDIV_MM  : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
87                 MULT_FM_MM<0x2ac>;
88  def UDIV_MM  : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
89                 MULT_FM_MM<0x2ec>;
90
91  /// Shift Instructions
92  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd>,
93                 SRA_FM_MM<0, 0>;
94  def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd>,
95                 SRA_FM_MM<0x40, 0>;
96  def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd>,
97                 SRA_FM_MM<0x80, 0>;
98  def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
99                 SRLV_FM_MM<0x10, 0>;
100  def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
101                 SRLV_FM_MM<0x50, 0>;
102  def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
103                 SRLV_FM_MM<0x90, 0>;
104  def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd>,
105                 SRA_FM_MM<0xc0, 0>;
106  def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
107                 SRLV_FM_MM<0xd0, 0>;
108
109  /// Load and Store Instructions - aligned
110  let DecoderMethod = "DecodeMemMMImm16" in {
111    def LB_MM  : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
112    def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
113    def LH_MM  : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
114    def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
115    def LW_MM  : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
116    def SB_MM  : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
117    def SH_MM  : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
118    def SW_MM  : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
119  }
120
121  /// Load and Store Instructions - unaligned
122  def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
123               LWL_FM_MM<0x0>;
124  def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
125               LWL_FM_MM<0x1>;
126  def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
127               LWL_FM_MM<0x8>;
128  def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
129               LWL_FM_MM<0x9>;
130
131  /// Move Conditional
132  def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
133                  NoItinerary>, ADD_FM_MM<0, 0x58>;
134  def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
135                  NoItinerary>, ADD_FM_MM<0, 0x18>;
136  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIAlu>,
137                  CMov_F_I_FM_MM<0x25>;
138  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIAlu>,
139                  CMov_F_I_FM_MM<0x5>;
140
141  /// Move to/from HI/LO
142  def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
143                MTLO_FM_MM<0x0b5>;
144  def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
145                MTLO_FM_MM<0x0f5>;
146  def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
147                MFLO_FM_MM<0x035>;
148  def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
149                MFLO_FM_MM<0x075>;
150
151  /// Multiply Add/Sub Instructions
152  def MADD_MM  : MMRel, MArithR<"madd", 1>, MULT_FM_MM<0x32c>;
153  def MADDU_MM : MMRel, MArithR<"maddu", 1>, MULT_FM_MM<0x36c>;
154  def MSUB_MM  : MMRel, MArithR<"msub">, MULT_FM_MM<0x3ac>;
155  def MSUBU_MM : MMRel, MArithR<"msubu">, MULT_FM_MM<0x3ec>;
156
157  /// Count Leading
158  def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>;
159  def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>;
160
161  /// Sign Ext In Register Instructions.
162  def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM_MM<0x0ac>;
163  def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM_MM<0x0ec>;
164
165  /// Word Swap Bytes Within Halfwords
166  def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>;
167
168  def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
169               EXT_FM_MM<0x2c>;
170  def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
171               EXT_FM_MM<0x0c>;
172
173  /// Jump Instructions
174  let DecoderMethod = "DecodeJumpTargetMM" in {
175    def J_MM        : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
176                      J_FM_MM<0x35>;
177    def JAL_MM      : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>;
178    def TAILCALL_MM : MMRel, JumpFJ<calltarget_mm, "j", MipsTailCall, imm,
179                                    "tcall">, J_FM_MM<0x3d>, IsTailCall;
180  }
181  def JR_MM   : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>;
182  def JALR_MM : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>;
183  def TAILCALL_R_MM : MMRel, JumpFR<"tcallr", GPR32Opnd, MipsTailCall>,
184                      JR_FM_MM<0x3c>, IsTailCall;
185  def RET_MM : MMRel, RetBase<"ret", GPR32Opnd>, JR_FM_MM<0x3c>;
186
187  /// Branch Instructions
188  def BEQ_MM  : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
189                BEQ_FM_MM<0x25>;
190  def BNE_MM  : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
191                BEQ_FM_MM<0x2d>;
192  def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
193                BGEZ_FM_MM<0x2>;
194  def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
195                BGEZ_FM_MM<0x6>;
196  def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
197                BGEZ_FM_MM<0x4>;
198  def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
199                BGEZ_FM_MM<0x0>;
200  def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
201                  BGEZAL_FM_MM<0x03>;
202  def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
203                  BGEZAL_FM_MM<0x01>;
204
205  /// Trap Instructions
206  def TEQ_MM  : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>;
207  def TGE_MM  : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>;
208  def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>;
209  def TLT_MM  : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>;
210  def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>;
211  def TNE_MM  : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>;
212}
213