MicroMipsInstrInfo.td revision ab48d10effb223de0c9516ccae616a80fef27df8 
1def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>;
2
3def simm12 : Operand<i32> {
4  let DecoderMethod = "DecodeSimm12";
5}
6
7def mem_mm_12 : Operand<i32> {
8  let PrintMethod = "printMemOperand";
9  let MIOperandInfo = (ops GPR32, simm12);
10  let EncoderMethod = "getMemEncodingMMImm12";
11  let ParserMatchClass = MipsMemAsmOperand;
12  let OperandType = "OPERAND_MEMORY";
13}
14
15let canFoldAsLoad = 1 in
16class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
17                      Operand MemOpnd> :
18  InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
19         !strconcat(opstr, "\t$rt, $addr"),
20         [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
21         NoItinerary, FrmI> {
22  let DecoderMethod = "DecodeMemMMImm12";
23  string Constraints = "$src = $rt";
24}
25
26class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
27                       Operand MemOpnd>:
28  InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
29         !strconcat(opstr, "\t$rt, $addr"),
30         [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
31  let DecoderMethod = "DecodeMemMMImm12";
32}
33
34let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
35  /// Arithmetic Instructions (ALU Immediate)
36  def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
37                 ADDI_FM_MM<0xc>;
38  def ADDi_MM  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
39                 ADDI_FM_MM<0x4>;
40  def SLTi_MM  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
41                 SLTI_FM_MM<0x24>;
42  def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
43                 SLTI_FM_MM<0x2c>;
44  def ANDi_MM  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
45                 ADDI_FM_MM<0x34>;
46  def ORi_MM   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>,
47                 ADDI_FM_MM<0x14>;
48  def XORi_MM  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>,
49                 ADDI_FM_MM<0x1c>;
50  def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
51
52  /// Arithmetic Instructions (3-Operand, R-Type)
53  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
54  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
55  def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
56  def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
57  def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
58  def SLT_MM   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
59  def SLTu_MM  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
60                 ADD_FM_MM<0, 0x390>;
61  def AND_MM   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IIAlu, and>,
62                 ADD_FM_MM<0, 0x250>;
63  def OR_MM    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IIAlu, or>,
64                 ADD_FM_MM<0, 0x290>;
65  def XOR_MM   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IIAlu, xor>,
66                 ADD_FM_MM<0, 0x310>;
67  def NOR_MM   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>;
68  def MULT_MM  : MMRel, Mult<"mult", IIImul, GPR32Opnd, [HI0, LO0]>,
69                 MULT_FM_MM<0x22c>;
70  def MULTu_MM : MMRel, Mult<"multu", IIImul, GPR32Opnd, [HI0, LO0]>,
71                 MULT_FM_MM<0x26c>;
72  def SDIV_MM  : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
73                 MULT_FM_MM<0x2ac>;
74  def UDIV_MM  : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
75                 MULT_FM_MM<0x2ec>;
76
77  /// Shift Instructions
78  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd>,
79                 SRA_FM_MM<0, 0>;
80  def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd>,
81                 SRA_FM_MM<0x40, 0>;
82  def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd>,
83                 SRA_FM_MM<0x80, 0>;
84  def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
85                 SRLV_FM_MM<0x10, 0>;
86  def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
87                 SRLV_FM_MM<0x50, 0>;
88  def SRAV_MM  : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
89                 SRLV_FM_MM<0x90, 0>;
90  def ROTR_MM  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd>,
91                 SRA_FM_MM<0xc0, 0>;
92  def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
93                 SRLV_FM_MM<0xd0, 0>;
94
95  /// Load and Store Instructions - aligned
96  let DecoderMethod = "DecodeMemMMImm16" in {
97    def LB_MM  : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>;
98    def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>;
99    def LH_MM  : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>;
100    def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>;
101    def LW_MM  : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>;
102    def SB_MM  : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>;
103    def SH_MM  : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>;
104    def SW_MM  : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>;
105  }
106
107  /// Load and Store Instructions - unaligned
108  def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
109               LWL_FM_MM<0x0>;
110  def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
111               LWL_FM_MM<0x1>;
112  def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
113               LWL_FM_MM<0x8>;
114  def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
115               LWL_FM_MM<0x9>;
116
117  /// Move Conditional
118  def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
119                  NoItinerary>, ADD_FM_MM<0, 0x58>;
120  def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
121                  NoItinerary>, ADD_FM_MM<0, 0x18>;
122  def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, IIAlu>,
123                  CMov_F_I_FM_MM<0x25>;
124  def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, IIAlu>,
125                  CMov_F_I_FM_MM<0x5>;
126
127  /// Move to/from HI/LO
128  def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
129                MTLO_FM_MM<0x0b5>;
130  def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
131                MTLO_FM_MM<0x0f5>;
132  def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>,
133                MFLO_FM_MM<0x035>;
134  def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>,
135                MFLO_FM_MM<0x075>;
136
137  /// Multiply Add/Sub Instructions
138  def MADD_MM  : MMRel, MArithR<"madd", 1>, MULT_FM_MM<0x32c>;
139  def MADDU_MM : MMRel, MArithR<"maddu", 1>, MULT_FM_MM<0x36c>;
140  def MSUB_MM  : MMRel, MArithR<"msub">, MULT_FM_MM<0x3ac>;
141  def MSUBU_MM : MMRel, MArithR<"msubu">, MULT_FM_MM<0x3ec>;
142
143  /// Count Leading
144  def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>;
145  def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>;
146
147  /// Sign Ext In Register Instructions.
148  def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM_MM<0x0ac>;
149  def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM_MM<0x0ec>;
150
151  /// Word Swap Bytes Within Halfwords
152  def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>;
153
154  def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>,
155               EXT_FM_MM<0x2c>;
156  def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>,
157               EXT_FM_MM<0x0c>;
158}
159