Mips.td revision 0301bc54ad23c9dff0370dffaf6eb3eabba42cc4
1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This is the top level entry point for the Mips target. 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// Register File, Calling Conv, Instruction Descriptions 20//===----------------------------------------------------------------------===// 21 22include "MipsRegisterInfo.td" 23include "MipsSchedule.td" 24include "MipsInstrInfo.td" 25include "MipsCallingConv.td" 26 27def MipsInstrInfo : InstrInfo; 28 29//===----------------------------------------------------------------------===// 30// Mips Subtarget features // 31//===----------------------------------------------------------------------===// 32 33def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 34 "General Purpose Registers are 64-bit wide.">; 35def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 36 "Support 64-bit FP registers.">; 37def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 38 "true", "Only supports single precision float">; 39def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", 40 "Enable o32 ABI">; 41def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", 42 "Enable n32 ABI">; 43def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", 44 "Enable n64 ABI">; 45def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", 46 "Enable eabi ABI">; 47def FeatureAndroid : SubtargetFeature<"android", "IsAndroid", "true", 48 "Target is android">; 49def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 50 "true", "Enable vector FPU instructions.">; 51def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", 52 "Enable 'signext in register' instructions.">; 53def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", 54 "Enable 'conditional move' instructions.">; 55def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true", 56 "Enable 'multiply add/sub' instructions.">; 57def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true", 58 "Enable 'min/max' instructions.">; 59def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", 60 "Enable 'byte/half swap' instructions.">; 61def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", 62 "Enable 'count leading bits' instructions.">; 63def FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true", 64 "Enable 'FP indexed load/store' instructions.">; 65def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 66 "Mips32 ISA Support", 67 [FeatureCondMov, FeatureBitCount]>; 68def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 69 "Mips32r2", "Mips32r2 ISA Support", 70 [FeatureMips32, FeatureSEInReg, FeatureSwap, 71 FeatureFPIdx]>; 72def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 73 "Mips64", "Mips64 ISA Support", 74 [FeatureGP64Bit, FeatureFP64Bit, 75 FeatureMips32, FeatureFPIdx]>; 76def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 77 "Mips64r2", "Mips64r2 ISA Support", 78 [FeatureMips64, FeatureMips32r2]>; 79 80def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 81 "Mips16 mode">; 82 83def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 84def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 85 "Mips DSP-R2 ASE", [FeatureDSP]>; 86 87//===----------------------------------------------------------------------===// 88// Mips processors supported. 89//===----------------------------------------------------------------------===// 90 91class Proc<string Name, list<SubtargetFeature> Features> 92 : Processor<Name, MipsGenericItineraries, Features>; 93 94def : Proc<"mips32", [FeatureMips32]>; 95def : Proc<"mips32r2", [FeatureMips32r2]>; 96def : Proc<"mips64", [FeatureMips64]>; 97def : Proc<"mips64r2", [FeatureMips64r2]>; 98def : Proc<"mips16", [FeatureMips16]>; 99 100def MipsAsmWriter : AsmWriter { 101 string AsmWriterClassName = "InstPrinter"; 102 bit isMCAsmWriter = 1; 103} 104 105def MipsAsmParser : AsmParser { 106 let ShouldEmitMatchRegisterName = 0; 107} 108 109def MipsAsmParserVariant : AsmParserVariant { 110 int Variant = 0; 111 112 // Recognize hard coded registers. 113 string RegisterPrefix = "$"; 114} 115 116def Mips : Target { 117 let InstructionSet = MipsInstrInfo; 118 let AssemblyParsers = [MipsAsmParser]; 119 let AssemblyWriters = [MipsAsmWriter]; 120 let AssemblyParserVariants = [MipsAsmParserVariant]; 121} 122