Mips.td revision 615a279f81e08e9c63fd5e411b33d39bfe593314
1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This is the top level entry point for the Mips target. 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// Register File, Calling Conv, Instruction Descriptions 20//===----------------------------------------------------------------------===// 21 22include "MipsRegisterInfo.td" 23include "MipsSchedule.td" 24include "MipsInstrInfo.td" 25include "MipsCallingConv.td" 26 27def MipsInstrInfo : InstrInfo; 28 29//===----------------------------------------------------------------------===// 30// Mips Subtarget features // 31//===----------------------------------------------------------------------===// 32 33def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16", 34 "Set stack alignment to 16-bytes.">; 35def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 36 "General Purpose Registers are 64-bit wide.">; 37def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 38 "Support 64-bit FP registers.", [StackAlign16]>; 39def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 40 "true", "Only supports single precision float">; 41def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", 42 "Enable o32 ABI">; 43def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", 44 "Enable n32 ABI">; 45def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", 46 "Enable n64 ABI">; 47def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", 48 "Enable eabi ABI">; 49def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 50 "true", "Enable vector FPU instructions.">; 51def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", 52 "Enable 'signext in register' instructions.">; 53def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", 54 "Enable 'conditional move' instructions.">; 55def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", 56 "Enable 'byte/half swap' instructions.">; 57def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", 58 "Enable 'count leading bits' instructions.">; 59def FeatureFPIdx : SubtargetFeature<"FPIdx", "HasFPIdx", "true", 60 "Enable 'FP indexed load/store' instructions.">; 61def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 62 "Mips32 ISA Support", 63 [FeatureCondMov, FeatureBitCount]>; 64def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 65 "Mips32r2", "Mips32r2 ISA Support", 66 [FeatureMips32, FeatureSEInReg, FeatureSwap, 67 FeatureFPIdx]>; 68def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 69 "Mips64", "Mips64 ISA Support", 70 [FeatureGP64Bit, FeatureFP64Bit, 71 FeatureMips32, FeatureFPIdx]>; 72def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 73 "Mips64r2", "Mips64r2 ISA Support", 74 [FeatureMips64, FeatureMips32r2]>; 75 76def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", 77 "Mips16 mode">; 78 79def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; 80def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", 81 "Mips DSP-R2 ASE", [FeatureDSP]>; 82 83def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; 84 85def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", 86 "microMips mode">; 87 88//===----------------------------------------------------------------------===// 89// Mips processors supported. 90//===----------------------------------------------------------------------===// 91 92class Proc<string Name, list<SubtargetFeature> Features> 93 : Processor<Name, MipsGenericItineraries, Features>; 94 95def : Proc<"mips32", [FeatureMips32]>; 96def : Proc<"mips32r2", [FeatureMips32r2]>; 97def : Proc<"mips64", [FeatureMips64]>; 98def : Proc<"mips64r2", [FeatureMips64r2]>; 99def : Proc<"mips16", [FeatureMips16]>; 100 101def MipsAsmWriter : AsmWriter { 102 string AsmWriterClassName = "InstPrinter"; 103 bit isMCAsmWriter = 1; 104} 105 106def MipsAsmParser : AsmParser { 107 let ShouldEmitMatchRegisterName = 0; 108 let MnemonicContainsDot = 1; 109} 110 111def MipsAsmParserVariant : AsmParserVariant { 112 int Variant = 0; 113 114 // Recognize hard coded registers. 115 string RegisterPrefix = "$"; 116} 117 118def Mips : Target { 119 let InstructionSet = MipsInstrInfo; 120 let AssemblyParsers = [MipsAsmParser]; 121 let AssemblyWriters = [MipsAsmWriter]; 122 let AssemblyParserVariants = [MipsAsmParserVariant]; 123} 124