Mips.td revision 64ed8e97f75b498a1ba13e08d6c633c75b7f05ec 
1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// Register File, Calling Conv, Instruction Descriptions
20//===----------------------------------------------------------------------===//
21
22include "MipsRegisterInfo.td"
23include "MipsSchedule.td"
24include "MipsInstrInfo.td"
25include "MipsCallingConv.td"
26
27def MipsInstrInfo : InstrInfo;
28
29//===----------------------------------------------------------------------===//
30// Mips Subtarget features                                                    //
31//===----------------------------------------------------------------------===//
32
33def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
34                                "General Purpose Registers are 64-bit wide.">;
35def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
36                                "Support 64-bit FP registers.">;
37def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
38                                "true", "Only supports single precision float">;
39def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
40                                "Enable o32 ABI">;
41def FeatureN32         : SubtargetFeature<"n32", "MipsABI", "N32",
42                                "Enable n32 ABI">;
43def FeatureN64         : SubtargetFeature<"n64", "MipsABI", "N64",
44                                "Enable n64 ABI">;
45def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
46                                "Enable eabi ABI">;
47def FeatureAndroid     : SubtargetFeature<"android", "IsAndroid", "true",
48                                "Target is android">;
49def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
50                                "true", "Enable vector FPU instructions.">;
51def FeatureSEInReg     : SubtargetFeature<"seinreg", "HasSEInReg", "true",
52                                "Enable 'signext in register' instructions.">;
53def FeatureCondMov     : SubtargetFeature<"condmov", "HasCondMov", "true",
54                                "Enable 'conditional move' instructions.">;
55def FeatureSwap        : SubtargetFeature<"swap", "HasSwap", "true",
56                                "Enable 'byte/half swap' instructions.">;
57def FeatureBitCount    : SubtargetFeature<"bitcount", "HasBitCount", "true",
58                                "Enable 'count leading bits' instructions.">;
59def FeatureFPIdx       : SubtargetFeature<"FPIdx", "HasFPIdx", "true",
60                                "Enable 'FP indexed load/store' instructions.">;
61def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
62                                "Mips32 ISA Support",
63                                [FeatureCondMov, FeatureBitCount]>;
64def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
65                                "Mips32r2", "Mips32r2 ISA Support",
66                                [FeatureMips32, FeatureSEInReg, FeatureSwap,
67                                 FeatureFPIdx]>;
68def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
69                                "Mips64", "Mips64 ISA Support",
70                                [FeatureGP64Bit, FeatureFP64Bit,
71                                 FeatureMips32, FeatureFPIdx]>;
72def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
73                                "Mips64r2", "Mips64r2 ISA Support",
74                                [FeatureMips64, FeatureMips32r2]>;
75
76def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
77                                      "Mips16 mode">;
78
79def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
80def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
81                                    "Mips DSP-R2 ASE", [FeatureDSP]>;
82
83//===----------------------------------------------------------------------===//
84// Mips processors supported.
85//===----------------------------------------------------------------------===//
86
87class Proc<string Name, list<SubtargetFeature> Features>
88 : Processor<Name, MipsGenericItineraries, Features>;
89
90def : Proc<"mips32", [FeatureMips32]>;
91def : Proc<"mips32r2", [FeatureMips32r2]>;
92def : Proc<"mips64", [FeatureMips64]>;
93def : Proc<"mips64r2", [FeatureMips64r2]>;
94def : Proc<"mips16", [FeatureMips16]>;
95
96def MipsAsmWriter : AsmWriter {
97  string AsmWriterClassName  = "InstPrinter";
98  bit isMCAsmWriter = 1;
99}
100
101def MipsAsmParser : AsmParser {
102  let ShouldEmitMatchRegisterName = 0;
103}
104
105def MipsAsmParserVariant : AsmParserVariant {
106  int Variant = 0;
107
108  // Recognize hard coded registers.
109  string RegisterPrefix = "$";
110}
111
112def Mips : Target {
113  let InstructionSet = MipsInstrInfo;
114  let AssemblyParsers = [MipsAsmParser];
115  let AssemblyWriters = [MipsAsmWriter];
116  let AssemblyParserVariants = [MipsAsmParserVariant];
117}
118