Mips.td revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the Mips target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18// The overall idea of the PredicateControl class is to chop the Predicates list
19// into subsets that are usually overridden independently. This allows
20// subclasses to partially override the predicates of their superclasses without
21// having to re-add all the existing predicates.
22class PredicateControl {
23  // Predicates for the encoding scheme in use such as HasStdEnc
24  list<Predicate> EncodingPredicates = [];
25  // Predicates for the GPR size such as IsGP64bit
26  list<Predicate> GPRPredicates = [];
27  // Predicates for the FGR size and layout such as IsFP64bit
28  list<Predicate> FGRPredicates = [];
29  // Predicates for the instruction group membership such as ISA's and ASE's
30  list<Predicate> InsnPredicates = [];
31  // Predicates for anything else
32  list<Predicate> AdditionalPredicates = [];
33  list<Predicate> Predicates = !listconcat(EncodingPredicates,
34                                           GPRPredicates,
35                                           FGRPredicates,
36                                           InsnPredicates,
37                                           AdditionalPredicates);
38}
39
40// Like Requires<> but for the AdditionalPredicates list
41class AdditionalRequires<list<Predicate> preds> {
42  list<Predicate> AdditionalPredicates = preds;
43}
44
45//===----------------------------------------------------------------------===//
46// Register File, Calling Conv, Instruction Descriptions
47//===----------------------------------------------------------------------===//
48
49include "MipsRegisterInfo.td"
50include "MipsSchedule.td"
51include "MipsInstrInfo.td"
52include "MipsCallingConv.td"
53
54def MipsInstrInfo : InstrInfo;
55
56//===----------------------------------------------------------------------===//
57// Mips Subtarget features                                                    //
58//===----------------------------------------------------------------------===//
59
60def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
61                                "General Purpose Registers are 64-bit wide.">;
62def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
63                                "Support 64-bit FP registers.">;
64def FeatureFPXX        : SubtargetFeature<"fpxx", "IsFPXX", "true",
65                                "Support for FPXX.">;
66def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
67                                "IEEE 754-2008 NaN encoding.">;
68def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
69                                "true", "Only supports single precision float">;
70def FeatureO32         : SubtargetFeature<"o32", "MipsABI", "O32",
71                                "Enable o32 ABI">;
72def FeatureN32         : SubtargetFeature<"n32", "MipsABI", "N32",
73                                "Enable n32 ABI">;
74def FeatureN64         : SubtargetFeature<"n64", "MipsABI", "N64",
75                                "Enable n64 ABI">;
76def FeatureEABI        : SubtargetFeature<"eabi", "MipsABI", "EABI",
77                                "Enable eabi ABI">;
78def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
79                              "Disable odd numbered single-precision "
80                              "registers">;
81def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
82                                "true", "Enable vector FPU instructions.">;
83def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
84                                "Mips I ISA Support [highly experimental]">;
85def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
86                                "Mips II ISA Support [highly experimental]",
87                                [FeatureMips1]>;
88def FeatureMips3_32    : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
89                                "Subset of MIPS-III that is also in MIPS32 "
90                                "[highly experimental]">;
91def FeatureMips3_32r2  : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
92                                "Subset of MIPS-III that is also in MIPS32r2 "
93                                "[highly experimental]">;
94def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
95                                "MIPS III ISA Support [highly experimental]",
96                                [FeatureMips2, FeatureMips3_32,
97                                 FeatureMips3_32r2, FeatureGP64Bit,
98                                 FeatureFP64Bit]>;
99def FeatureMips4_32    : SubtargetFeature<"mips4_32", "HasMips4_32", "true",
100                                "Subset of MIPS-IV that is also in MIPS32 "
101                                "[highly experimental]">;
102def FeatureMips4_32r2  : SubtargetFeature<"mips4_32r2", "HasMips4_32r2", "true",
103                                "Subset of MIPS-IV that is also in MIPS32r2 "
104                                "[highly experimental]">;
105def FeatureMips4       : SubtargetFeature<"mips4", "MipsArchVersion",
106                                "Mips4", "MIPS IV ISA Support",
107                                [FeatureMips3, FeatureMips4_32,
108                                 FeatureMips4_32r2]>;
109def FeatureMips5_32r2  : SubtargetFeature<"mips5_32r2", "HasMips5_32r2", "true",
110                                "Subset of MIPS-V that is also in MIPS32r2 "
111                                "[highly experimental]">;
112def FeatureMips5       : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
113                                "MIPS V ISA Support [highly experimental]",
114                                [FeatureMips4, FeatureMips5_32r2]>;
115def FeatureMips32      : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
116                                "Mips32 ISA Support",
117                                [FeatureMips2, FeatureMips3_32,
118                                 FeatureMips4_32]>;
119def FeatureMips32r2    : SubtargetFeature<"mips32r2", "MipsArchVersion",
120                                "Mips32r2", "Mips32r2 ISA Support",
121                                [FeatureMips3_32r2, FeatureMips4_32r2,
122                                 FeatureMips5_32r2, FeatureMips32]>;
123def FeatureMips32r6    : SubtargetFeature<"mips32r6", "MipsArchVersion",
124                                "Mips32r6",
125                                "Mips32r6 ISA Support [experimental]",
126                                [FeatureMips32r2, FeatureFP64Bit,
127                                 FeatureNaN2008]>;
128def FeatureMips64      : SubtargetFeature<"mips64", "MipsArchVersion",
129                                "Mips64", "Mips64 ISA Support",
130                                [FeatureMips5, FeatureMips32]>;
131def FeatureMips64r2    : SubtargetFeature<"mips64r2", "MipsArchVersion",
132                                "Mips64r2", "Mips64r2 ISA Support",
133                                [FeatureMips64, FeatureMips32r2]>;
134def FeatureMips64r6    : SubtargetFeature<"mips64r6", "MipsArchVersion",
135                                "Mips64r6",
136                                "Mips64r6 ISA Support [experimental]",
137                                [FeatureMips32r6, FeatureMips64r2,
138                                 FeatureNaN2008]>;
139
140def FeatureMips16  : SubtargetFeature<"mips16", "InMips16Mode", "true",
141                                      "Mips16 mode">;
142
143def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
144def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
145                                    "Mips DSP-R2 ASE", [FeatureDSP]>;
146
147def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
148
149def FeatureMicroMips  : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
150                                         "microMips mode">;
151
152def FeatureCnMips     : SubtargetFeature<"cnmips", "HasCnMips",
153                                "true", "Octeon cnMIPS Support",
154                                [FeatureMips64r2]>;
155
156//===----------------------------------------------------------------------===//
157// Mips processors supported.
158//===----------------------------------------------------------------------===//
159
160class Proc<string Name, list<SubtargetFeature> Features>
161 : Processor<Name, MipsGenericItineraries, Features>;
162
163def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
164def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
165def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
166def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
167def : Proc<"mips32r6", [FeatureMips32r6, FeatureO32]>;
168
169def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
170def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
171def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
172def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
173def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
174def : Proc<"mips64r6", [FeatureMips64r6, FeatureN64]>;
175def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
176def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
177
178def MipsAsmParser : AsmParser {
179  let ShouldEmitMatchRegisterName = 0;
180  let MnemonicContainsDot = 1;
181}
182
183def MipsAsmParserVariant : AsmParserVariant {
184  int Variant = 0;
185
186  // Recognize hard coded registers.
187  string RegisterPrefix = "$";
188}
189
190def Mips : Target {
191  let InstructionSet = MipsInstrInfo;
192  let AssemblyParsers = [MipsAsmParser];
193  let AssemblyParserVariants = [MipsAsmParserVariant];
194}
195