Mips16ISelLowering.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips16.
11//
12//===----------------------------------------------------------------------===//
13#define DEBUG_TYPE "mips-lower"
14#include "Mips16ISelLowering.h"
15#include "MCTargetDesc/MipsBaseInfo.h"
16#include "MipsRegisterInfo.h"
17#include "MipsTargetMachine.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include <string>
23
24using namespace llvm;
25
26static cl::opt<bool> DontExpandCondPseudos16(
27  "mips16-dont-expand-cond-pseudo",
28  cl::init(false),
29  cl::desc("Dont expand conditional move related "
30           "pseudos for Mips 16"),
31  cl::Hidden);
32
33namespace {
34struct Mips16Libcall {
35  RTLIB::Libcall Libcall;
36  const char *Name;
37
38  bool operator<(const Mips16Libcall &RHS) const {
39    return std::strcmp(Name, RHS.Name) < 0;
40  }
41};
42
43struct Mips16IntrinsicHelperType{
44  const char* Name;
45  const char* Helper;
46
47  bool operator<(const Mips16IntrinsicHelperType &RHS) const {
48    return std::strcmp(Name, RHS.Name) < 0;
49  }
50  bool operator==(const Mips16IntrinsicHelperType &RHS) const {
51    return std::strcmp(Name, RHS.Name) == 0;
52  }
53};
54}
55
56// Libcalls for which no helper is generated. Sorted by name for binary search.
57static const Mips16Libcall HardFloatLibCalls[] = {
58  { RTLIB::ADD_F64, "__mips16_adddf3" },
59  { RTLIB::ADD_F32, "__mips16_addsf3" },
60  { RTLIB::DIV_F64, "__mips16_divdf3" },
61  { RTLIB::DIV_F32, "__mips16_divsf3" },
62  { RTLIB::OEQ_F64, "__mips16_eqdf2" },
63  { RTLIB::OEQ_F32, "__mips16_eqsf2" },
64  { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" },
65  { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" },
66  { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" },
67  { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" },
68  { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" },
69  { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" },
70  { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" },
71  { RTLIB::OGE_F64, "__mips16_gedf2" },
72  { RTLIB::OGE_F32, "__mips16_gesf2" },
73  { RTLIB::OGT_F64, "__mips16_gtdf2" },
74  { RTLIB::OGT_F32, "__mips16_gtsf2" },
75  { RTLIB::OLE_F64, "__mips16_ledf2" },
76  { RTLIB::OLE_F32, "__mips16_lesf2" },
77  { RTLIB::OLT_F64, "__mips16_ltdf2" },
78  { RTLIB::OLT_F32, "__mips16_ltsf2" },
79  { RTLIB::MUL_F64, "__mips16_muldf3" },
80  { RTLIB::MUL_F32, "__mips16_mulsf3" },
81  { RTLIB::UNE_F64, "__mips16_nedf2" },
82  { RTLIB::UNE_F32, "__mips16_nesf2" },
83  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall.
84  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall.
85  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall.
86  { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall.
87  { RTLIB::SUB_F64, "__mips16_subdf3" },
88  { RTLIB::SUB_F32, "__mips16_subsf3" },
89  { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" },
90  { RTLIB::UO_F64, "__mips16_unorddf2" },
91  { RTLIB::UO_F32, "__mips16_unordsf2" }
92};
93
94static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
95  {"__fixunsdfsi", "__mips16_call_stub_2" },
96  {"ceil",  "__mips16_call_stub_df_2"},
97  {"ceilf", "__mips16_call_stub_sf_1"},
98  {"copysign",  "__mips16_call_stub_df_10"},
99  {"copysignf", "__mips16_call_stub_sf_5"},
100  {"cos",  "__mips16_call_stub_df_2"},
101  {"cosf", "__mips16_call_stub_sf_1"},
102  {"exp2",  "__mips16_call_stub_df_2"},
103  {"exp2f", "__mips16_call_stub_sf_1"},
104  {"floor",  "__mips16_call_stub_df_2"},
105  {"floorf", "__mips16_call_stub_sf_1"},
106  {"log2",  "__mips16_call_stub_df_2"},
107  {"log2f", "__mips16_call_stub_sf_1"},
108  {"nearbyint",  "__mips16_call_stub_df_2"},
109  {"nearbyintf", "__mips16_call_stub_sf_1"},
110  {"rint",  "__mips16_call_stub_df_2"},
111  {"rintf", "__mips16_call_stub_sf_1"},
112  {"sin",  "__mips16_call_stub_df_2"},
113  {"sinf", "__mips16_call_stub_sf_1"},
114  {"sqrt",  "__mips16_call_stub_df_2"},
115  {"sqrtf", "__mips16_call_stub_sf_1"},
116  {"trunc",  "__mips16_call_stub_df_2"},
117  {"truncf", "__mips16_call_stub_sf_1"},
118};
119
120Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM)
121  : MipsTargetLowering(TM) {
122  //
123  // set up as if mips32 and then revert so we can test the mechanism
124  // for switching
125  addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
126  addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
127  computeRegisterProperties();
128  clearRegisterClasses();
129
130  // Set up the register classes
131  addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
132
133  if (Subtarget->inMips16HardFloat())
134    setMips16HardFloatLibCalls();
135
136  setOperationAction(ISD::ATOMIC_FENCE,       MVT::Other, Expand);
137  setOperationAction(ISD::ATOMIC_CMP_SWAP,    MVT::i32,   Expand);
138  setOperationAction(ISD::ATOMIC_SWAP,        MVT::i32,   Expand);
139  setOperationAction(ISD::ATOMIC_LOAD_ADD,    MVT::i32,   Expand);
140  setOperationAction(ISD::ATOMIC_LOAD_SUB,    MVT::i32,   Expand);
141  setOperationAction(ISD::ATOMIC_LOAD_AND,    MVT::i32,   Expand);
142  setOperationAction(ISD::ATOMIC_LOAD_OR,     MVT::i32,   Expand);
143  setOperationAction(ISD::ATOMIC_LOAD_XOR,    MVT::i32,   Expand);
144  setOperationAction(ISD::ATOMIC_LOAD_NAND,   MVT::i32,   Expand);
145  setOperationAction(ISD::ATOMIC_LOAD_MIN,    MVT::i32,   Expand);
146  setOperationAction(ISD::ATOMIC_LOAD_MAX,    MVT::i32,   Expand);
147  setOperationAction(ISD::ATOMIC_LOAD_UMIN,   MVT::i32,   Expand);
148  setOperationAction(ISD::ATOMIC_LOAD_UMAX,   MVT::i32,   Expand);
149
150  setOperationAction(ISD::ROTR, MVT::i32,  Expand);
151  setOperationAction(ISD::ROTR, MVT::i64,  Expand);
152  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
153  setOperationAction(ISD::BSWAP, MVT::i64, Expand);
154
155  computeRegisterProperties();
156}
157
158const MipsTargetLowering *
159llvm::createMips16TargetLowering(MipsTargetMachine &TM) {
160  return new Mips16TargetLowering(TM);
161}
162
163bool
164Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
165                                                    unsigned,
166                                                    bool *Fast) const {
167  return false;
168}
169
170MachineBasicBlock *
171Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
172                                                  MachineBasicBlock *BB) const {
173  switch (MI->getOpcode()) {
174  default:
175    return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
176  case Mips::SelBeqZ:
177    return emitSel16(Mips::BeqzRxImm16, MI, BB);
178  case Mips::SelBneZ:
179    return emitSel16(Mips::BnezRxImm16, MI, BB);
180  case Mips::SelTBteqZCmpi:
181    return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB);
182  case Mips::SelTBteqZSlti:
183    return emitSeliT16(Mips::Bteqz16, Mips::SltiRxImmX16, MI, BB);
184  case Mips::SelTBteqZSltiu:
185    return emitSeliT16(Mips::Bteqz16, Mips::SltiuRxImmX16, MI, BB);
186  case Mips::SelTBtneZCmpi:
187    return emitSeliT16(Mips::Btnez16, Mips::CmpiRxImmX16, MI, BB);
188  case Mips::SelTBtneZSlti:
189    return emitSeliT16(Mips::Btnez16, Mips::SltiRxImmX16, MI, BB);
190  case Mips::SelTBtneZSltiu:
191    return emitSeliT16(Mips::Btnez16, Mips::SltiuRxImmX16, MI, BB);
192  case Mips::SelTBteqZCmp:
193    return emitSelT16(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
194  case Mips::SelTBteqZSlt:
195    return emitSelT16(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
196  case Mips::SelTBteqZSltu:
197    return emitSelT16(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
198  case Mips::SelTBtneZCmp:
199    return emitSelT16(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
200  case Mips::SelTBtneZSlt:
201    return emitSelT16(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
202  case Mips::SelTBtneZSltu:
203    return emitSelT16(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
204  case Mips::BteqzT8CmpX16:
205    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::CmpRxRy16, MI, BB);
206  case Mips::BteqzT8SltX16:
207    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltRxRy16, MI, BB);
208  case Mips::BteqzT8SltuX16:
209    // TBD: figure out a way to get this or remove the instruction
210    // altogether.
211    return emitFEXT_T8I816_ins(Mips::Bteqz16, Mips::SltuRxRy16, MI, BB);
212  case Mips::BtnezT8CmpX16:
213    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::CmpRxRy16, MI, BB);
214  case Mips::BtnezT8SltX16:
215    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltRxRy16, MI, BB);
216  case Mips::BtnezT8SltuX16:
217    // TBD: figure out a way to get this or remove the instruction
218    // altogether.
219    return emitFEXT_T8I816_ins(Mips::Btnez16, Mips::SltuRxRy16, MI, BB);
220  case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
221    Mips::Bteqz16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
222  case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
223    Mips::Bteqz16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
224  case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
225    Mips::Bteqz16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
226  case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
227    Mips::Btnez16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB);
228  case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
229    Mips::Btnez16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB);
230  case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
231    Mips::Btnez16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB);
232    break;
233  case Mips::SltCCRxRy16:
234    return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB);
235    break;
236  case Mips::SltiCCRxImmX16:
237    return emitFEXT_CCRXI16_ins
238      (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB);
239  case Mips::SltiuCCRxImmX16:
240    return emitFEXT_CCRXI16_ins
241      (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB);
242  case Mips::SltuCCRxRy16:
243    return emitFEXT_CCRX16_ins
244      (Mips::SltuRxRy16, MI, BB);
245  }
246}
247
248bool Mips16TargetLowering::
249isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
250                                  unsigned NextStackOffset,
251                                  const MipsFunctionInfo& FI) const {
252  // No tail call optimization for mips16.
253  return false;
254}
255
256void Mips16TargetLowering::setMips16HardFloatLibCalls() {
257  for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) {
258    assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
259           "Array not sorted!");
260    if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL)
261      setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name);
262  }
263
264  setLibcallName(RTLIB::O_F64, "__mips16_unorddf2");
265  setLibcallName(RTLIB::O_F32, "__mips16_unordsf2");
266}
267
268//
269// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
270// cleaner way to do all of this but it will have to wait until the traditional
271// gcc mechanism is completed.
272//
273// For Pic, in order for Mips16 code to call Mips32 code which according the abi
274// have either arguments or returned values placed in floating point registers,
275// we use a set of helper functions. (This includes functions which return type
276//  complex which on Mips are returned in a pair of floating point registers).
277//
278// This is an encoding that we inherited from gcc.
279// In Mips traditional O32, N32 ABI, floating point numbers are passed in
280// floating point argument registers 1,2 only when the first and optionally
281// the second arguments are float (sf) or double (df).
282// For Mips16 we are only concerned with the situations where floating point
283// arguments are being passed in floating point registers by the ABI, because
284// Mips16 mode code cannot execute floating point instructions to load those
285// values and hence helper functions are needed.
286// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
287// the helper function suffixs for these are:
288//                        0,  1,    5,        9,         2,   6,        10
289// this suffix can then be calculated as follows:
290// for a given argument Arg:
291//     Arg1x, Arg2x = 1 :  Arg is sf
292//                    2 :  Arg is df
293//                    0:   Arg is neither sf or df
294// So this stub is the string for number Arg1x + Arg2x*4.
295// However not all numbers between 0 and 10 are possible, we check anyway and
296// assert if the impossible exists.
297//
298
299unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
300  (ArgListTy &Args) const {
301  unsigned int resultNum = 0;
302  if (Args.size() >= 1) {
303    Type *t = Args[0].Ty;
304    if (t->isFloatTy()) {
305      resultNum = 1;
306    }
307    else if (t->isDoubleTy()) {
308      resultNum = 2;
309    }
310  }
311  if (resultNum) {
312    if (Args.size() >=2) {
313      Type *t = Args[1].Ty;
314      if (t->isFloatTy()) {
315        resultNum += 4;
316      }
317      else if (t->isDoubleTy()) {
318        resultNum += 8;
319      }
320    }
321  }
322  return resultNum;
323}
324
325//
326// prefixs are attached to stub numbers depending on the return type .
327// return type: float  sf_
328//              double df_
329//              single complex sc_
330//              double complext dc_
331//              others  NO PREFIX
332//
333//
334// The full name of a helper function is__mips16_call_stub +
335//    return type dependent prefix + stub number
336//
337//
338// This is something that probably should be in a different source file and
339// perhaps done differently but my main purpose is to not waste runtime
340// on something that we can enumerate in the source. Another possibility is
341// to have a python script to generate these mapping tables. This will do
342// for now. There are a whole series of helper function mapping arrays, one
343// for each return type class as outlined above. There there are 11 possible
344//  entries. Ones with 0 are ones which should never be selected
345//
346// All the arrays are similar except for ones which return neither
347// sf, df, sc, dc, in which only care about ones which have sf or df as a
348// first parameter.
349//
350#define P_ "__mips16_call_stub_"
351#define MAX_STUB_NUMBER 10
352#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
353#define T P "0" , T1
354#define P P_
355static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
356  {0, T1 };
357#undef P
358#define P P_ "sf_"
359static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
360  { T };
361#undef P
362#define P P_ "df_"
363static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
364  { T };
365#undef P
366#define P P_ "sc_"
367static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
368  { T };
369#undef P
370#define P P_ "dc_"
371static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
372  { T };
373#undef P
374#undef P_
375
376
377const char* Mips16TargetLowering::
378  getMips16HelperFunction
379    (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
380  const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
381#ifndef NDEBUG
382  const unsigned int maxStubNum = 10;
383  assert(stubNum <= maxStubNum);
384  const bool validStubNum[maxStubNum+1] =
385    {true, true, true, false, false, true, true, false, false, true, true};
386  assert(validStubNum[stubNum]);
387#endif
388  const char *result;
389  if (RetTy->isFloatTy()) {
390    result = sfMips16Helper[stubNum];
391  }
392  else if (RetTy ->isDoubleTy()) {
393    result = dfMips16Helper[stubNum];
394  }
395  else if (RetTy->isStructTy()) {
396    // check if it's complex
397    if (RetTy->getNumContainedTypes() == 2) {
398      if ((RetTy->getContainedType(0)->isFloatTy()) &&
399          (RetTy->getContainedType(1)->isFloatTy())) {
400        result = scMips16Helper[stubNum];
401      }
402      else if ((RetTy->getContainedType(0)->isDoubleTy()) &&
403               (RetTy->getContainedType(1)->isDoubleTy())) {
404        result = dcMips16Helper[stubNum];
405      }
406      else {
407        llvm_unreachable("Uncovered condition");
408      }
409    }
410    else {
411      llvm_unreachable("Uncovered condition");
412    }
413  }
414  else {
415    if (stubNum == 0) {
416      needHelper = false;
417      return "";
418    }
419    result = vMips16Helper[stubNum];
420  }
421  needHelper = true;
422  return result;
423}
424
425void Mips16TargetLowering::
426getOpndList(SmallVectorImpl<SDValue> &Ops,
427            std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
428            bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
429            CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
430  SelectionDAG &DAG = CLI.DAG;
431  MachineFunction &MF = DAG.getMachineFunction();
432  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
433  const char* Mips16HelperFunction = 0;
434  bool NeedMips16Helper = false;
435
436  if (Subtarget->inMips16HardFloat()) {
437    //
438    // currently we don't have symbols tagged with the mips16 or mips32
439    // qualifier so we will assume that we don't know what kind it is.
440    // and generate the helper
441    //
442    bool LookupHelper = true;
443    if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
444      Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() };
445
446      if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls),
447                             Find))
448        LookupHelper = false;
449      else {
450        const char *Symbol = S->getSymbol();
451        Mips16IntrinsicHelperType IntrinsicFind = { Symbol, "" };
452        const Mips16HardFloatInfo::FuncSignature *Signature =
453            Mips16HardFloatInfo::findFuncSignature(Symbol);
454        if (!IsPICCall && (Signature && (FuncInfo->StubsNeeded.find(Symbol) ==
455                                         FuncInfo->StubsNeeded.end()))) {
456          FuncInfo->StubsNeeded[Symbol] = Signature;
457          //
458          // S2 is normally saved if the stub is for a function which
459          // returns a float or double value and is not otherwise. This is
460          // because more work is required after the function the stub
461          // is calling completes, and so the stub cannot directly return
462          // and the stub has no stack space to store the return address so
463          // S2 is used for that purpose.
464          // In order to take advantage of not saving S2, we need to also
465          // optimize the call in the stub and this requires some further
466          // functionality in MipsAsmPrinter which we don't have yet.
467          // So for now we always save S2. The optimization will be done
468          // in a follow-on patch.
469          //
470          if (1 || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
471            FuncInfo->setSaveS2();
472        }
473        // one more look at list of intrinsics
474        if (std::binary_search(Mips16IntrinsicHelper,
475            array_endof(Mips16IntrinsicHelper),
476                                     IntrinsicFind)) {
477          const Mips16IntrinsicHelperType *h =(std::find(Mips16IntrinsicHelper,
478              array_endof(Mips16IntrinsicHelper),
479                                       IntrinsicFind));
480          Mips16HelperFunction = h->Helper;
481          NeedMips16Helper = true;
482          LookupHelper = false;
483        }
484
485      }
486    } else if (GlobalAddressSDNode *G =
487                   dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
488      Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL,
489                             G->getGlobal()->getName().data() };
490
491      if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls),
492                             Find))
493        LookupHelper = false;
494    }
495    if (LookupHelper) Mips16HelperFunction =
496      getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper);
497
498  }
499
500  SDValue JumpTarget = Callee;
501
502  // T9 should contain the address of the callee function if
503  // -reloction-model=pic or it is an indirect call.
504  if (IsPICCall || !GlobalOrExternal) {
505    unsigned V0Reg = Mips::V0;
506    if (NeedMips16Helper) {
507      RegsToPass.push_front(std::make_pair(V0Reg, Callee));
508      JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy());
509      ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget);
510      JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG,
511                                 MipsII::MO_GOT, Chain,
512                                 FuncInfo->callPtrInfo(S->getSymbol()));
513    } else
514      RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
515  }
516
517  Ops.push_back(JumpTarget);
518
519  MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
520                                  InternalLinkage, CLI, Callee, Chain);
521}
522
523MachineBasicBlock *Mips16TargetLowering::
524emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const {
525  if (DontExpandCondPseudos16)
526    return BB;
527  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
528  DebugLoc DL = MI->getDebugLoc();
529  // To "insert" a SELECT_CC instruction, we actually have to insert the
530  // diamond control-flow pattern.  The incoming instruction knows the
531  // destination vreg to set, the condition code register to branch on, the
532  // true/false values to select between, and a branch opcode to use.
533  const BasicBlock *LLVM_BB = BB->getBasicBlock();
534  MachineFunction::iterator It = BB;
535  ++It;
536
537  //  thisMBB:
538  //  ...
539  //   TrueVal = ...
540  //   setcc r1, r2, r3
541  //   bNE   r1, r0, copy1MBB
542  //   fallthrough --> copy0MBB
543  MachineBasicBlock *thisMBB  = BB;
544  MachineFunction *F = BB->getParent();
545  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
546  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
547  F->insert(It, copy0MBB);
548  F->insert(It, sinkMBB);
549
550  // Transfer the remainder of BB and its successor edges to sinkMBB.
551  sinkMBB->splice(sinkMBB->begin(), BB,
552                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
553  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
554
555  // Next, add the true and fallthrough blocks as its successors.
556  BB->addSuccessor(copy0MBB);
557  BB->addSuccessor(sinkMBB);
558
559  BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
560    .addMBB(sinkMBB);
561
562  //  copy0MBB:
563  //   %FalseValue = ...
564  //   # fallthrough to sinkMBB
565  BB = copy0MBB;
566
567  // Update machine-CFG edges
568  BB->addSuccessor(sinkMBB);
569
570  //  sinkMBB:
571  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
572  //  ...
573  BB = sinkMBB;
574
575  BuildMI(*BB, BB->begin(), DL,
576          TII->get(Mips::PHI), MI->getOperand(0).getReg())
577    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
578    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
579
580  MI->eraseFromParent();   // The pseudo instruction is gone now.
581  return BB;
582}
583
584MachineBasicBlock *Mips16TargetLowering::emitSelT16
585  (unsigned Opc1, unsigned Opc2,
586   MachineInstr *MI, MachineBasicBlock *BB) const {
587  if (DontExpandCondPseudos16)
588    return BB;
589  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
590  DebugLoc DL = MI->getDebugLoc();
591  // To "insert" a SELECT_CC instruction, we actually have to insert the
592  // diamond control-flow pattern.  The incoming instruction knows the
593  // destination vreg to set, the condition code register to branch on, the
594  // true/false values to select between, and a branch opcode to use.
595  const BasicBlock *LLVM_BB = BB->getBasicBlock();
596  MachineFunction::iterator It = BB;
597  ++It;
598
599  //  thisMBB:
600  //  ...
601  //   TrueVal = ...
602  //   setcc r1, r2, r3
603  //   bNE   r1, r0, copy1MBB
604  //   fallthrough --> copy0MBB
605  MachineBasicBlock *thisMBB  = BB;
606  MachineFunction *F = BB->getParent();
607  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
608  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
609  F->insert(It, copy0MBB);
610  F->insert(It, sinkMBB);
611
612  // Transfer the remainder of BB and its successor edges to sinkMBB.
613  sinkMBB->splice(sinkMBB->begin(), BB,
614                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
615  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
616
617  // Next, add the true and fallthrough blocks as its successors.
618  BB->addSuccessor(copy0MBB);
619  BB->addSuccessor(sinkMBB);
620
621  BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
622    .addReg(MI->getOperand(4).getReg());
623  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
624
625  //  copy0MBB:
626  //   %FalseValue = ...
627  //   # fallthrough to sinkMBB
628  BB = copy0MBB;
629
630  // Update machine-CFG edges
631  BB->addSuccessor(sinkMBB);
632
633  //  sinkMBB:
634  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
635  //  ...
636  BB = sinkMBB;
637
638  BuildMI(*BB, BB->begin(), DL,
639          TII->get(Mips::PHI), MI->getOperand(0).getReg())
640    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
641    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
642
643  MI->eraseFromParent();   // The pseudo instruction is gone now.
644  return BB;
645
646}
647
648MachineBasicBlock *Mips16TargetLowering::emitSeliT16
649  (unsigned Opc1, unsigned Opc2,
650   MachineInstr *MI, MachineBasicBlock *BB) const {
651  if (DontExpandCondPseudos16)
652    return BB;
653  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
654  DebugLoc DL = MI->getDebugLoc();
655  // To "insert" a SELECT_CC instruction, we actually have to insert the
656  // diamond control-flow pattern.  The incoming instruction knows the
657  // destination vreg to set, the condition code register to branch on, the
658  // true/false values to select between, and a branch opcode to use.
659  const BasicBlock *LLVM_BB = BB->getBasicBlock();
660  MachineFunction::iterator It = BB;
661  ++It;
662
663  //  thisMBB:
664  //  ...
665  //   TrueVal = ...
666  //   setcc r1, r2, r3
667  //   bNE   r1, r0, copy1MBB
668  //   fallthrough --> copy0MBB
669  MachineBasicBlock *thisMBB  = BB;
670  MachineFunction *F = BB->getParent();
671  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
672  MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
673  F->insert(It, copy0MBB);
674  F->insert(It, sinkMBB);
675
676  // Transfer the remainder of BB and its successor edges to sinkMBB.
677  sinkMBB->splice(sinkMBB->begin(), BB,
678                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
679  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
680
681  // Next, add the true and fallthrough blocks as its successors.
682  BB->addSuccessor(copy0MBB);
683  BB->addSuccessor(sinkMBB);
684
685  BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
686    .addImm(MI->getOperand(4).getImm());
687  BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
688
689  //  copy0MBB:
690  //   %FalseValue = ...
691  //   # fallthrough to sinkMBB
692  BB = copy0MBB;
693
694  // Update machine-CFG edges
695  BB->addSuccessor(sinkMBB);
696
697  //  sinkMBB:
698  //   %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
699  //  ...
700  BB = sinkMBB;
701
702  BuildMI(*BB, BB->begin(), DL,
703          TII->get(Mips::PHI), MI->getOperand(0).getReg())
704    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
705    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
706
707  MI->eraseFromParent();   // The pseudo instruction is gone now.
708  return BB;
709
710}
711
712MachineBasicBlock
713  *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
714                                             MachineInstr *MI,
715                                             MachineBasicBlock *BB) const {
716  if (DontExpandCondPseudos16)
717    return BB;
718  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
719  unsigned regX = MI->getOperand(0).getReg();
720  unsigned regY = MI->getOperand(1).getReg();
721  MachineBasicBlock *target = MI->getOperand(2).getMBB();
722  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
723    .addReg(regY);
724  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
725  MI->eraseFromParent();   // The pseudo instruction is gone now.
726  return BB;
727}
728
729MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
730  unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
731  MachineInstr *MI,  MachineBasicBlock *BB) const {
732  if (DontExpandCondPseudos16)
733    return BB;
734  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
735  unsigned regX = MI->getOperand(0).getReg();
736  int64_t imm = MI->getOperand(1).getImm();
737  MachineBasicBlock *target = MI->getOperand(2).getMBB();
738  unsigned CmpOpc;
739  if (isUInt<8>(imm))
740    CmpOpc = CmpiOpc;
741  else if ((!ImmSigned && isUInt<16>(imm)) ||
742           (ImmSigned && isInt<16>(imm)))
743    CmpOpc = CmpiXOpc;
744  else
745    llvm_unreachable("immediate field not usable");
746  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX)
747    .addImm(imm);
748  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target);
749  MI->eraseFromParent();   // The pseudo instruction is gone now.
750  return BB;
751}
752
753static unsigned Mips16WhichOp8uOr16simm
754  (unsigned shortOp, unsigned longOp, int64_t Imm) {
755  if (isUInt<8>(Imm))
756    return shortOp;
757  else if (isInt<16>(Imm))
758    return longOp;
759  else
760    llvm_unreachable("immediate field not usable");
761}
762
763MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins(
764  unsigned SltOpc,
765  MachineInstr *MI,  MachineBasicBlock *BB) const {
766  if (DontExpandCondPseudos16)
767    return BB;
768  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
769  unsigned CC = MI->getOperand(0).getReg();
770  unsigned regX = MI->getOperand(1).getReg();
771  unsigned regY = MI->getOperand(2).getReg();
772  BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(SltOpc)).addReg(regX).addReg(
773      regY);
774  BuildMI(*BB, MI, MI->getDebugLoc(),
775          TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
776  MI->eraseFromParent();   // The pseudo instruction is gone now.
777  return BB;
778}
779
780MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins(
781  unsigned SltiOpc, unsigned SltiXOpc,
782  MachineInstr *MI,  MachineBasicBlock *BB )const {
783  if (DontExpandCondPseudos16)
784    return BB;
785  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
786  unsigned CC = MI->getOperand(0).getReg();
787  unsigned regX = MI->getOperand(1).getReg();
788  int64_t Imm = MI->getOperand(2).getImm();
789  unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm);
790  BuildMI(*BB, MI, MI->getDebugLoc(),
791          TII->get(SltOpc)).addReg(regX).addImm(Imm);
792  BuildMI(*BB, MI, MI->getDebugLoc(),
793          TII->get(Mips::MoveR3216), CC).addReg(Mips::T8);
794  MI->eraseFromParent();   // The pseudo instruction is gone now.
795  return BB;
796
797}
798