Mips16ISelLowering.cpp revision 793803449870a661c1a09e400df9b04492772196
1//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsTargetLowering specialized for mips16. 11// 12//===----------------------------------------------------------------------===// 13#define DEBUG_TYPE "mips-lower" 14#include "Mips16ISelLowering.h" 15#include "MipsRegisterInfo.h" 16#include "MipsTargetMachine.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Target/TargetInstrInfo.h" 21 22using namespace llvm; 23 24static cl::opt<bool> DontExpandCondPseudos16( 25 "mips16-dont-expand-cond-pseudo", 26 cl::init(false), 27 cl::desc("Dont expand conditional move related " 28 "pseudos for Mips 16"), 29 cl::Hidden); 30 31namespace { 32struct Mips16Libcall { 33 RTLIB::Libcall Libcall; 34 const char *Name; 35 36 bool operator<(const Mips16Libcall &RHS) const { 37 return std::strcmp(Name, RHS.Name) < 0; 38 } 39}; 40 41struct Mips16IntrinsicHelperType{ 42 const char* Name; 43 const char* Helper; 44 45 bool operator<(const Mips16IntrinsicHelperType &RHS) const { 46 return std::strcmp(Name, RHS.Name) < 0; 47 } 48 bool operator==(const Mips16IntrinsicHelperType &RHS) const { 49 return std::strcmp(Name, RHS.Name) == 0; 50 } 51}; 52} 53 54// Libcalls for which no helper is generated. Sorted by name for binary search. 55static const Mips16Libcall HardFloatLibCalls[] = { 56 { RTLIB::ADD_F64, "__mips16_adddf3" }, 57 { RTLIB::ADD_F32, "__mips16_addsf3" }, 58 { RTLIB::DIV_F64, "__mips16_divdf3" }, 59 { RTLIB::DIV_F32, "__mips16_divsf3" }, 60 { RTLIB::OEQ_F64, "__mips16_eqdf2" }, 61 { RTLIB::OEQ_F32, "__mips16_eqsf2" }, 62 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" }, 63 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" }, 64 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" }, 65 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" }, 66 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" }, 67 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" }, 68 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" }, 69 { RTLIB::OGE_F64, "__mips16_gedf2" }, 70 { RTLIB::OGE_F32, "__mips16_gesf2" }, 71 { RTLIB::OGT_F64, "__mips16_gtdf2" }, 72 { RTLIB::OGT_F32, "__mips16_gtsf2" }, 73 { RTLIB::OLE_F64, "__mips16_ledf2" }, 74 { RTLIB::OLE_F32, "__mips16_lesf2" }, 75 { RTLIB::OLT_F64, "__mips16_ltdf2" }, 76 { RTLIB::OLT_F32, "__mips16_ltsf2" }, 77 { RTLIB::MUL_F64, "__mips16_muldf3" }, 78 { RTLIB::MUL_F32, "__mips16_mulsf3" }, 79 { RTLIB::UNE_F64, "__mips16_nedf2" }, 80 { RTLIB::UNE_F32, "__mips16_nesf2" }, 81 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall. 82 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall. 83 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall. 84 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall. 85 { RTLIB::SUB_F64, "__mips16_subdf3" }, 86 { RTLIB::SUB_F32, "__mips16_subsf3" }, 87 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" }, 88 { RTLIB::UO_F64, "__mips16_unorddf2" }, 89 { RTLIB::UO_F32, "__mips16_unordsf2" } 90}; 91 92static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = { 93 {"__fixunsdfsi", "__mips16_call_stub_2" }, 94 {"ceil", "__mips16_call_stub_df_2"}, 95 {"ceilf", "__mips16_call_stub_sf_1"}, 96 {"copysign", "__mips16_call_stub_df_10"}, 97 {"copysignf", "__mips16_call_stub_sf_5"}, 98 {"cos", "__mips16_call_stub_df_2"}, 99 {"cosf", "__mips16_call_stub_sf_1"}, 100 {"exp2", "__mips16_call_stub_df_2"}, 101 {"exp2f", "__mips16_call_stub_sf_1"}, 102 {"floor", "__mips16_call_stub_df_2"}, 103 {"floorf", "__mips16_call_stub_sf_1"}, 104 {"log2", "__mips16_call_stub_df_2"}, 105 {"log2f", "__mips16_call_stub_sf_1"}, 106 {"nearbyint", "__mips16_call_stub_df_2"}, 107 {"nearbyintf", "__mips16_call_stub_sf_1"}, 108 {"rint", "__mips16_call_stub_df_2"}, 109 {"rintf", "__mips16_call_stub_sf_1"}, 110 {"sin", "__mips16_call_stub_df_2"}, 111 {"sinf", "__mips16_call_stub_sf_1"}, 112 {"sqrt", "__mips16_call_stub_df_2"}, 113 {"sqrtf", "__mips16_call_stub_sf_1"}, 114 {"trunc", "__mips16_call_stub_df_2"}, 115 {"truncf", "__mips16_call_stub_sf_1"}, 116}; 117 118Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) 119 : MipsTargetLowering(TM) { 120 // 121 // set up as if mips32 and then revert so we can test the mechanism 122 // for switching 123 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 124 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 125 computeRegisterProperties(); 126 clearRegisterClasses(); 127 128 // Set up the register classes 129 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 130 131 if (Subtarget->inMips16HardFloat()) 132 setMips16HardFloatLibCalls(); 133 134 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 135 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 136 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 137 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 138 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 139 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 140 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 141 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 142 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 143 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 144 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 145 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 146 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 147 148 computeRegisterProperties(); 149} 150 151const MipsTargetLowering * 152llvm::createMips16TargetLowering(MipsTargetMachine &TM) { 153 return new Mips16TargetLowering(TM); 154} 155 156bool 157Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 158 return false; 159} 160 161MachineBasicBlock * 162Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 163 MachineBasicBlock *BB) const { 164 switch (MI->getOpcode()) { 165 default: 166 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 167 case Mips::SelBeqZ: 168 return emitSel16(Mips::BeqzRxImm16, MI, BB); 169 case Mips::SelBneZ: 170 return emitSel16(Mips::BnezRxImm16, MI, BB); 171 case Mips::SelTBteqZCmpi: 172 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB); 173 case Mips::SelTBteqZSlti: 174 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB); 175 case Mips::SelTBteqZSltiu: 176 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB); 177 case Mips::SelTBtneZCmpi: 178 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB); 179 case Mips::SelTBtneZSlti: 180 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB); 181 case Mips::SelTBtneZSltiu: 182 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB); 183 case Mips::SelTBteqZCmp: 184 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 185 case Mips::SelTBteqZSlt: 186 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 187 case Mips::SelTBteqZSltu: 188 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 189 case Mips::SelTBtneZCmp: 190 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 191 case Mips::SelTBtneZSlt: 192 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 193 case Mips::SelTBtneZSltu: 194 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 195 case Mips::BteqzT8CmpX16: 196 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 197 case Mips::BteqzT8SltX16: 198 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 199 case Mips::BteqzT8SltuX16: 200 // TBD: figure out a way to get this or remove the instruction 201 // altogether. 202 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 203 case Mips::BtnezT8CmpX16: 204 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 205 case Mips::BtnezT8SltX16: 206 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 207 case Mips::BtnezT8SltuX16: 208 // TBD: figure out a way to get this or remove the instruction 209 // altogether. 210 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 211 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins( 212 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 213 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins( 214 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 215 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins( 216 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 217 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins( 218 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 219 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins( 220 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 221 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins( 222 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 223 break; 224 case Mips::SltCCRxRy16: 225 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB); 226 break; 227 case Mips::SltiCCRxImmX16: 228 return emitFEXT_CCRXI16_ins 229 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 230 case Mips::SltiuCCRxImmX16: 231 return emitFEXT_CCRXI16_ins 232 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 233 case Mips::SltuCCRxRy16: 234 return emitFEXT_CCRX16_ins 235 (Mips::SltuRxRy16, MI, BB); 236 } 237} 238 239bool Mips16TargetLowering:: 240isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 241 unsigned NextStackOffset, 242 const MipsFunctionInfo& FI) const { 243 // No tail call optimization for mips16. 244 return false; 245} 246 247void Mips16TargetLowering::setMips16HardFloatLibCalls() { 248 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) { 249 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) && 250 "Array not sorted!"); 251 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL) 252 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name); 253 } 254 255 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2"); 256 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2"); 257} 258 259// 260// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much 261// cleaner way to do all of this but it will have to wait until the traditional 262// gcc mechanism is completed. 263// 264// For Pic, in order for Mips16 code to call Mips32 code which according the abi 265// have either arguments or returned values placed in floating point registers, 266// we use a set of helper functions. (This includes functions which return type 267// complex which on Mips are returned in a pair of floating point registers). 268// 269// This is an encoding that we inherited from gcc. 270// In Mips traditional O32, N32 ABI, floating point numbers are passed in 271// floating point argument registers 1,2 only when the first and optionally 272// the second arguments are float (sf) or double (df). 273// For Mips16 we are only concerned with the situations where floating point 274// arguments are being passed in floating point registers by the ABI, because 275// Mips16 mode code cannot execute floating point instructions to load those 276// values and hence helper functions are needed. 277// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df) 278// the helper function suffixs for these are: 279// 0, 1, 5, 9, 2, 6, 10 280// this suffix can then be calculated as follows: 281// for a given argument Arg: 282// Arg1x, Arg2x = 1 : Arg is sf 283// 2 : Arg is df 284// 0: Arg is neither sf or df 285// So this stub is the string for number Arg1x + Arg2x*4. 286// However not all numbers between 0 and 10 are possible, we check anyway and 287// assert if the impossible exists. 288// 289 290unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber 291 (ArgListTy &Args) const { 292 unsigned int resultNum = 0; 293 if (Args.size() >= 1) { 294 Type *t = Args[0].Ty; 295 if (t->isFloatTy()) { 296 resultNum = 1; 297 } 298 else if (t->isDoubleTy()) { 299 resultNum = 2; 300 } 301 } 302 if (resultNum) { 303 if (Args.size() >=2) { 304 Type *t = Args[1].Ty; 305 if (t->isFloatTy()) { 306 resultNum += 4; 307 } 308 else if (t->isDoubleTy()) { 309 resultNum += 8; 310 } 311 } 312 } 313 return resultNum; 314} 315 316// 317// prefixs are attached to stub numbers depending on the return type . 318// return type: float sf_ 319// double df_ 320// single complex sc_ 321// double complext dc_ 322// others NO PREFIX 323// 324// 325// The full name of a helper function is__mips16_call_stub + 326// return type dependent prefix + stub number 327// 328// 329// This is something that probably should be in a different source file and 330// perhaps done differently but my main purpose is to not waste runtime 331// on something that we can enumerate in the source. Another possibility is 332// to have a python script to generate these mapping tables. This will do 333// for now. There are a whole series of helper function mapping arrays, one 334// for each return type class as outlined above. There there are 11 possible 335// entries. Ones with 0 are ones which should never be selected 336// 337// All the arrays are similar except for ones which return neither 338// sf, df, sc, dc, in which only care about ones which have sf or df as a 339// first parameter. 340// 341#define P_ "__mips16_call_stub_" 342#define MAX_STUB_NUMBER 10 343#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10" 344#define T P "0" , T1 345#define P P_ 346static char const * vMips16Helper[MAX_STUB_NUMBER+1] = 347 {0, T1 }; 348#undef P 349#define P P_ "sf_" 350static char const * sfMips16Helper[MAX_STUB_NUMBER+1] = 351 { T }; 352#undef P 353#define P P_ "df_" 354static char const * dfMips16Helper[MAX_STUB_NUMBER+1] = 355 { T }; 356#undef P 357#define P P_ "sc_" 358static char const * scMips16Helper[MAX_STUB_NUMBER+1] = 359 { T }; 360#undef P 361#define P P_ "dc_" 362static char const * dcMips16Helper[MAX_STUB_NUMBER+1] = 363 { T }; 364#undef P 365#undef P_ 366 367 368const char* Mips16TargetLowering:: 369 getMips16HelperFunction 370 (Type* RetTy, ArgListTy &Args, bool &needHelper) const { 371 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); 372#ifndef NDEBUG 373 const unsigned int maxStubNum = 10; 374 assert(stubNum <= maxStubNum); 375 const bool validStubNum[maxStubNum+1] = 376 {true, true, true, false, false, true, true, false, false, true, true}; 377 assert(validStubNum[stubNum]); 378#endif 379 const char *result; 380 if (RetTy->isFloatTy()) { 381 result = sfMips16Helper[stubNum]; 382 } 383 else if (RetTy ->isDoubleTy()) { 384 result = dfMips16Helper[stubNum]; 385 } 386 else if (RetTy->isStructTy()) { 387 // check if it's complex 388 if (RetTy->getNumContainedTypes() == 2) { 389 if ((RetTy->getContainedType(0)->isFloatTy()) && 390 (RetTy->getContainedType(1)->isFloatTy())) { 391 result = scMips16Helper[stubNum]; 392 } 393 else if ((RetTy->getContainedType(0)->isDoubleTy()) && 394 (RetTy->getContainedType(1)->isDoubleTy())) { 395 result = dcMips16Helper[stubNum]; 396 } 397 else { 398 llvm_unreachable("Uncovered condition"); 399 } 400 } 401 else { 402 llvm_unreachable("Uncovered condition"); 403 } 404 } 405 else { 406 if (stubNum == 0) { 407 needHelper = false; 408 return ""; 409 } 410 result = vMips16Helper[stubNum]; 411 } 412 needHelper = true; 413 return result; 414} 415 416void Mips16TargetLowering:: 417getOpndList(SmallVectorImpl<SDValue> &Ops, 418 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 419 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 420 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 421 SelectionDAG &DAG = CLI.DAG; 422 const char* Mips16HelperFunction = 0; 423 bool NeedMips16Helper = false; 424 425 if (getTargetMachine().Options.UseSoftFloat && 426 Subtarget->inMips16HardFloat()) { 427 // 428 // currently we don't have symbols tagged with the mips16 or mips32 429 // qualifier so we will assume that we don't know what kind it is. 430 // and generate the helper 431 // 432 bool LookupHelper = true; 433 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) { 434 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() }; 435 436 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 437 Find)) 438 LookupHelper = false; 439 else { 440 Mips16IntrinsicHelperType IntrinsicFind = {S->getSymbol(), ""}; 441 // one more look at list of intrinsics 442 if (std::binary_search(Mips16IntrinsicHelper, 443 array_endof(Mips16IntrinsicHelper), 444 IntrinsicFind)) { 445 const Mips16IntrinsicHelperType *h =(std::find(Mips16IntrinsicHelper, 446 array_endof(Mips16IntrinsicHelper), 447 IntrinsicFind)); 448 Mips16HelperFunction = h->Helper; 449 NeedMips16Helper = true; 450 LookupHelper = false; 451 } 452 453 } 454 } else if (GlobalAddressSDNode *G = 455 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 456 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, 457 G->getGlobal()->getName().data() }; 458 459 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 460 Find)) 461 LookupHelper = false; 462 } 463 if (LookupHelper) Mips16HelperFunction = 464 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper); 465 466 } 467 468 SDValue JumpTarget = Callee; 469 470 // T9 should contain the address of the callee function if 471 // -reloction-model=pic or it is an indirect call. 472 if (IsPICCall || !GlobalOrExternal) { 473 unsigned V0Reg = Mips::V0; 474 if (NeedMips16Helper) { 475 RegsToPass.push_front(std::make_pair(V0Reg, Callee)); 476 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy()); 477 JumpTarget = getAddrGlobal(cast<ExternalSymbolSDNode>(JumpTarget), 478 JumpTarget.getValueType(), DAG, 479 MipsII::MO_GOT); 480 } else 481 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee)); 482 } 483 484 Ops.push_back(JumpTarget); 485 486 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 487 InternalLinkage, CLI, Callee, Chain); 488} 489 490MachineBasicBlock *Mips16TargetLowering:: 491emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { 492 if (DontExpandCondPseudos16) 493 return BB; 494 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 495 DebugLoc DL = MI->getDebugLoc(); 496 // To "insert" a SELECT_CC instruction, we actually have to insert the 497 // diamond control-flow pattern. The incoming instruction knows the 498 // destination vreg to set, the condition code register to branch on, the 499 // true/false values to select between, and a branch opcode to use. 500 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 501 MachineFunction::iterator It = BB; 502 ++It; 503 504 // thisMBB: 505 // ... 506 // TrueVal = ... 507 // setcc r1, r2, r3 508 // bNE r1, r0, copy1MBB 509 // fallthrough --> copy0MBB 510 MachineBasicBlock *thisMBB = BB; 511 MachineFunction *F = BB->getParent(); 512 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 513 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 514 F->insert(It, copy0MBB); 515 F->insert(It, sinkMBB); 516 517 // Transfer the remainder of BB and its successor edges to sinkMBB. 518 sinkMBB->splice(sinkMBB->begin(), BB, 519 llvm::next(MachineBasicBlock::iterator(MI)), 520 BB->end()); 521 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 522 523 // Next, add the true and fallthrough blocks as its successors. 524 BB->addSuccessor(copy0MBB); 525 BB->addSuccessor(sinkMBB); 526 527 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) 528 .addMBB(sinkMBB); 529 530 // copy0MBB: 531 // %FalseValue = ... 532 // # fallthrough to sinkMBB 533 BB = copy0MBB; 534 535 // Update machine-CFG edges 536 BB->addSuccessor(sinkMBB); 537 538 // sinkMBB: 539 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 540 // ... 541 BB = sinkMBB; 542 543 BuildMI(*BB, BB->begin(), DL, 544 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 545 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 546 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 547 548 MI->eraseFromParent(); // The pseudo instruction is gone now. 549 return BB; 550} 551 552MachineBasicBlock *Mips16TargetLowering::emitSelT16 553 (unsigned Opc1, unsigned Opc2, 554 MachineInstr *MI, MachineBasicBlock *BB) const { 555 if (DontExpandCondPseudos16) 556 return BB; 557 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 558 DebugLoc DL = MI->getDebugLoc(); 559 // To "insert" a SELECT_CC instruction, we actually have to insert the 560 // diamond control-flow pattern. The incoming instruction knows the 561 // destination vreg to set, the condition code register to branch on, the 562 // true/false values to select between, and a branch opcode to use. 563 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 564 MachineFunction::iterator It = BB; 565 ++It; 566 567 // thisMBB: 568 // ... 569 // TrueVal = ... 570 // setcc r1, r2, r3 571 // bNE r1, r0, copy1MBB 572 // fallthrough --> copy0MBB 573 MachineBasicBlock *thisMBB = BB; 574 MachineFunction *F = BB->getParent(); 575 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 576 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 577 F->insert(It, copy0MBB); 578 F->insert(It, sinkMBB); 579 580 // Transfer the remainder of BB and its successor edges to sinkMBB. 581 sinkMBB->splice(sinkMBB->begin(), BB, 582 llvm::next(MachineBasicBlock::iterator(MI)), 583 BB->end()); 584 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 585 586 // Next, add the true and fallthrough blocks as its successors. 587 BB->addSuccessor(copy0MBB); 588 BB->addSuccessor(sinkMBB); 589 590 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 591 .addReg(MI->getOperand(4).getReg()); 592 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 593 594 // copy0MBB: 595 // %FalseValue = ... 596 // # fallthrough to sinkMBB 597 BB = copy0MBB; 598 599 // Update machine-CFG edges 600 BB->addSuccessor(sinkMBB); 601 602 // sinkMBB: 603 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 604 // ... 605 BB = sinkMBB; 606 607 BuildMI(*BB, BB->begin(), DL, 608 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 609 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 610 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 611 612 MI->eraseFromParent(); // The pseudo instruction is gone now. 613 return BB; 614 615} 616 617MachineBasicBlock *Mips16TargetLowering::emitSeliT16 618 (unsigned Opc1, unsigned Opc2, 619 MachineInstr *MI, MachineBasicBlock *BB) const { 620 if (DontExpandCondPseudos16) 621 return BB; 622 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 623 DebugLoc DL = MI->getDebugLoc(); 624 // To "insert" a SELECT_CC instruction, we actually have to insert the 625 // diamond control-flow pattern. The incoming instruction knows the 626 // destination vreg to set, the condition code register to branch on, the 627 // true/false values to select between, and a branch opcode to use. 628 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 629 MachineFunction::iterator It = BB; 630 ++It; 631 632 // thisMBB: 633 // ... 634 // TrueVal = ... 635 // setcc r1, r2, r3 636 // bNE r1, r0, copy1MBB 637 // fallthrough --> copy0MBB 638 MachineBasicBlock *thisMBB = BB; 639 MachineFunction *F = BB->getParent(); 640 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 641 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 642 F->insert(It, copy0MBB); 643 F->insert(It, sinkMBB); 644 645 // Transfer the remainder of BB and its successor edges to sinkMBB. 646 sinkMBB->splice(sinkMBB->begin(), BB, 647 llvm::next(MachineBasicBlock::iterator(MI)), 648 BB->end()); 649 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 650 651 // Next, add the true and fallthrough blocks as its successors. 652 BB->addSuccessor(copy0MBB); 653 BB->addSuccessor(sinkMBB); 654 655 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 656 .addImm(MI->getOperand(4).getImm()); 657 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 658 659 // copy0MBB: 660 // %FalseValue = ... 661 // # fallthrough to sinkMBB 662 BB = copy0MBB; 663 664 // Update machine-CFG edges 665 BB->addSuccessor(sinkMBB); 666 667 // sinkMBB: 668 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 669 // ... 670 BB = sinkMBB; 671 672 BuildMI(*BB, BB->begin(), DL, 673 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 674 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 675 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 676 677 MI->eraseFromParent(); // The pseudo instruction is gone now. 678 return BB; 679 680} 681 682MachineBasicBlock 683 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 684 MachineInstr *MI, 685 MachineBasicBlock *BB) const { 686 if (DontExpandCondPseudos16) 687 return BB; 688 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 689 unsigned regX = MI->getOperand(0).getReg(); 690 unsigned regY = MI->getOperand(1).getReg(); 691 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 692 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 693 .addReg(regY); 694 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 695 MI->eraseFromParent(); // The pseudo instruction is gone now. 696 return BB; 697} 698 699MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( 700 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, 701 MachineInstr *MI, MachineBasicBlock *BB) const { 702 if (DontExpandCondPseudos16) 703 return BB; 704 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 705 unsigned regX = MI->getOperand(0).getReg(); 706 int64_t imm = MI->getOperand(1).getImm(); 707 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 708 unsigned CmpOpc; 709 if (isUInt<8>(imm)) 710 CmpOpc = CmpiOpc; 711 else if ((!ImmSigned && isUInt<16>(imm)) || 712 (ImmSigned && isInt<16>(imm))) 713 CmpOpc = CmpiXOpc; 714 else 715 llvm_unreachable("immediate field not usable"); 716 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 717 .addImm(imm); 718 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 719 MI->eraseFromParent(); // The pseudo instruction is gone now. 720 return BB; 721} 722 723static unsigned Mips16WhichOp8uOr16simm 724 (unsigned shortOp, unsigned longOp, int64_t Imm) { 725 if (isUInt<8>(Imm)) 726 return shortOp; 727 else if (isInt<16>(Imm)) 728 return longOp; 729 else 730 llvm_unreachable("immediate field not usable"); 731} 732 733MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( 734 unsigned SltOpc, 735 MachineInstr *MI, MachineBasicBlock *BB) const { 736 if (DontExpandCondPseudos16) 737 return BB; 738 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 739 unsigned CC = MI->getOperand(0).getReg(); 740 unsigned regX = MI->getOperand(1).getReg(); 741 unsigned regY = MI->getOperand(2).getReg(); 742 BuildMI(*BB, MI, MI->getDebugLoc(), 743 TII->get(SltOpc)).addReg(regX).addReg(regY); 744 BuildMI(*BB, MI, MI->getDebugLoc(), 745 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 746 MI->eraseFromParent(); // The pseudo instruction is gone now. 747 return BB; 748} 749 750MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins( 751 unsigned SltiOpc, unsigned SltiXOpc, 752 MachineInstr *MI, MachineBasicBlock *BB )const { 753 if (DontExpandCondPseudos16) 754 return BB; 755 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 756 unsigned CC = MI->getOperand(0).getReg(); 757 unsigned regX = MI->getOperand(1).getReg(); 758 int64_t Imm = MI->getOperand(2).getImm(); 759 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 760 BuildMI(*BB, MI, MI->getDebugLoc(), 761 TII->get(SltOpc)).addReg(regX).addImm(Imm); 762 BuildMI(*BB, MI, MI->getDebugLoc(), 763 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 764 MI->eraseFromParent(); // The pseudo instruction is gone now. 765 return BB; 766 767} 768