Mips16ISelLowering.cpp revision 90cd06e90be1db06bc4812ae9ec96b6638847285
1//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsTargetLowering specialized for mips16. 11// 12//===----------------------------------------------------------------------===// 13#define DEBUG_TYPE "mips-lower" 14#include "Mips16ISelLowering.h" 15#include "MipsRegisterInfo.h" 16#include "MipsTargetMachine.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Target/TargetInstrInfo.h" 21 22using namespace llvm; 23 24static cl::opt<bool> DontExpandCondPseudos16( 25 "mips16-dont-expand-cond-pseudo", 26 cl::init(false), 27 cl::desc("Dont expand conditional move related " 28 "pseudos for Mips 16"), 29 cl::Hidden); 30 31namespace { 32struct Mips16Libcall { 33 RTLIB::Libcall Libcall; 34 const char *Name; 35 36 bool operator<(const Mips16Libcall &RHS) const { 37 return std::strcmp(Name, RHS.Name) < 0; 38 } 39}; 40} 41 42// Libcalls for which no helper is generated. Sorted by name for binary search. 43static const Mips16Libcall HardFloatLibCalls[] = { 44 { RTLIB::ADD_F64, "__mips16_adddf3" }, 45 { RTLIB::ADD_F32, "__mips16_addsf3" }, 46 { RTLIB::DIV_F64, "__mips16_divdf3" }, 47 { RTLIB::DIV_F32, "__mips16_divsf3" }, 48 { RTLIB::OEQ_F64, "__mips16_eqdf2" }, 49 { RTLIB::OEQ_F32, "__mips16_eqsf2" }, 50 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" }, 51 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" }, 52 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" }, 53 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" }, 54 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" }, 55 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" }, 56 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" }, 57 { RTLIB::OGE_F64, "__mips16_gedf2" }, 58 { RTLIB::OGE_F32, "__mips16_gesf2" }, 59 { RTLIB::OGT_F64, "__mips16_gtdf2" }, 60 { RTLIB::OGT_F32, "__mips16_gtsf2" }, 61 { RTLIB::OLE_F64, "__mips16_ledf2" }, 62 { RTLIB::OLE_F32, "__mips16_lesf2" }, 63 { RTLIB::OLT_F64, "__mips16_ltdf2" }, 64 { RTLIB::OLT_F32, "__mips16_ltsf2" }, 65 { RTLIB::MUL_F64, "__mips16_muldf3" }, 66 { RTLIB::MUL_F32, "__mips16_mulsf3" }, 67 { RTLIB::UNE_F64, "__mips16_nedf2" }, 68 { RTLIB::UNE_F32, "__mips16_nesf2" }, 69 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall. 70 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall. 71 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall. 72 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall. 73 { RTLIB::SUB_F64, "__mips16_subdf3" }, 74 { RTLIB::SUB_F32, "__mips16_subsf3" }, 75 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" }, 76 { RTLIB::UO_F64, "__mips16_unorddf2" }, 77 { RTLIB::UO_F32, "__mips16_unordsf2" } 78}; 79 80Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) 81 : MipsTargetLowering(TM) { 82 // 83 // set up as if mips32 and then revert so we can test the mechanism 84 // for switching 85 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 86 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 87 computeRegisterProperties(); 88 clearRegisterClasses(); 89 90 // Set up the register classes 91 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 92 93 if (Subtarget->inMips16HardFloat()) 94 setMips16HardFloatLibCalls(); 95 96 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 97 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 98 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 99 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 100 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 101 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 102 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 103 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 104 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 105 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 106 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 107 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 108 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 109 110 computeRegisterProperties(); 111} 112 113const MipsTargetLowering * 114llvm::createMips16TargetLowering(MipsTargetMachine &TM) { 115 return new Mips16TargetLowering(TM); 116} 117 118bool 119Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 120 return false; 121} 122 123MachineBasicBlock * 124Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 125 MachineBasicBlock *BB) const { 126 switch (MI->getOpcode()) { 127 default: 128 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 129 case Mips::SelBeqZ: 130 return emitSel16(Mips::BeqzRxImm16, MI, BB); 131 case Mips::SelBneZ: 132 return emitSel16(Mips::BnezRxImm16, MI, BB); 133 case Mips::SelTBteqZCmpi: 134 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB); 135 case Mips::SelTBteqZSlti: 136 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB); 137 case Mips::SelTBteqZSltiu: 138 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB); 139 case Mips::SelTBtneZCmpi: 140 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB); 141 case Mips::SelTBtneZSlti: 142 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB); 143 case Mips::SelTBtneZSltiu: 144 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB); 145 case Mips::SelTBteqZCmp: 146 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 147 case Mips::SelTBteqZSlt: 148 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 149 case Mips::SelTBteqZSltu: 150 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 151 case Mips::SelTBtneZCmp: 152 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 153 case Mips::SelTBtneZSlt: 154 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 155 case Mips::SelTBtneZSltu: 156 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 157 case Mips::BteqzT8CmpX16: 158 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 159 case Mips::BteqzT8SltX16: 160 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 161 case Mips::BteqzT8SltuX16: 162 // TBD: figure out a way to get this or remove the instruction 163 // altogether. 164 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 165 case Mips::BtnezT8CmpX16: 166 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 167 case Mips::BtnezT8SltX16: 168 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 169 case Mips::BtnezT8SltuX16: 170 // TBD: figure out a way to get this or remove the instruction 171 // altogether. 172 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 173 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins( 174 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 175 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins( 176 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 177 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins( 178 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 179 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins( 180 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 181 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins( 182 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 183 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins( 184 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 185 break; 186 case Mips::SltCCRxRy16: 187 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB); 188 break; 189 case Mips::SltiCCRxImmX16: 190 return emitFEXT_CCRXI16_ins 191 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 192 case Mips::SltiuCCRxImmX16: 193 return emitFEXT_CCRXI16_ins 194 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 195 case Mips::SltuCCRxRy16: 196 return emitFEXT_CCRX16_ins 197 (Mips::SltuRxRy16, MI, BB); 198 } 199} 200 201bool Mips16TargetLowering:: 202isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 203 unsigned NextStackOffset, 204 const MipsFunctionInfo& FI) const { 205 // No tail call optimization for mips16. 206 return false; 207} 208 209void Mips16TargetLowering::setMips16HardFloatLibCalls() { 210 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) { 211 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) && 212 "Array not sorted!"); 213 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL) 214 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name); 215 } 216 217 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2"); 218 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2"); 219} 220 221// 222// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much 223// cleaner way to do all of this but it will have to wait until the traditional 224// gcc mechanism is completed. 225// 226// For Pic, in order for Mips16 code to call Mips32 code which according the abi 227// have either arguments or returned values placed in floating point registers, 228// we use a set of helper functions. (This includes functions which return type 229// complex which on Mips are returned in a pair of floating point registers). 230// 231// This is an encoding that we inherited from gcc. 232// In Mips traditional O32, N32 ABI, floating point numbers are passed in 233// floating point argument registers 1,2 only when the first and optionally 234// the second arguments are float (sf) or double (df). 235// For Mips16 we are only concerned with the situations where floating point 236// arguments are being passed in floating point registers by the ABI, because 237// Mips16 mode code cannot execute floating point instructions to load those 238// values and hence helper functions are needed. 239// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df) 240// the helper function suffixs for these are: 241// 0, 1, 5, 9, 2, 6, 10 242// this suffix can then be calculated as follows: 243// for a given argument Arg: 244// Arg1x, Arg2x = 1 : Arg is sf 245// 2 : Arg is df 246// 0: Arg is neither sf or df 247// So this stub is the string for number Arg1x + Arg2x*4. 248// However not all numbers between 0 and 10 are possible, we check anyway and 249// assert if the impossible exists. 250// 251 252unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber 253 (ArgListTy &Args) const { 254 unsigned int resultNum = 0; 255 if (Args.size() >= 1) { 256 Type *t = Args[0].Ty; 257 if (t->isFloatTy()) { 258 resultNum = 1; 259 } 260 else if (t->isDoubleTy()) { 261 resultNum = 2; 262 } 263 } 264 if (resultNum) { 265 if (Args.size() >=2) { 266 Type *t = Args[1].Ty; 267 if (t->isFloatTy()) { 268 resultNum += 4; 269 } 270 else if (t->isDoubleTy()) { 271 resultNum += 8; 272 } 273 } 274 } 275 return resultNum; 276} 277 278// 279// prefixs are attached to stub numbers depending on the return type . 280// return type: float sf_ 281// double df_ 282// single complex sc_ 283// double complext dc_ 284// others NO PREFIX 285// 286// 287// The full name of a helper function is__mips16_call_stub + 288// return type dependent prefix + stub number 289// 290// 291// This is something that probably should be in a different source file and 292// perhaps done differently but my main purpose is to not waste runtime 293// on something that we can enumerate in the source. Another possibility is 294// to have a python script to generate these mapping tables. This will do 295// for now. There are a whole series of helper function mapping arrays, one 296// for each return type class as outlined above. There there are 11 possible 297// entries. Ones with 0 are ones which should never be selected 298// 299// All the arrays are similar except for ones which return neither 300// sf, df, sc, dc, in which only care about ones which have sf or df as a 301// first parameter. 302// 303#define P_ "__mips16_call_stub_" 304#define MAX_STUB_NUMBER 10 305#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10" 306#define T P "0" , T1 307#define P P_ 308static char const * vMips16Helper[MAX_STUB_NUMBER+1] = 309 {0, T1 }; 310#undef P 311#define P P_ "sf_" 312static char const * sfMips16Helper[MAX_STUB_NUMBER+1] = 313 { T }; 314#undef P 315#define P P_ "df_" 316static char const * dfMips16Helper[MAX_STUB_NUMBER+1] = 317 { T }; 318#undef P 319#define P P_ "sc_" 320static char const * scMips16Helper[MAX_STUB_NUMBER+1] = 321 { T }; 322#undef P 323#define P P_ "dc_" 324static char const * dcMips16Helper[MAX_STUB_NUMBER+1] = 325 { T }; 326#undef P 327#undef P_ 328 329 330const char* Mips16TargetLowering:: 331 getMips16HelperFunction 332 (Type* RetTy, ArgListTy &Args, bool &needHelper) const { 333 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); 334#ifndef NDEBUG 335 const unsigned int maxStubNum = 10; 336 assert(stubNum <= maxStubNum); 337 const bool validStubNum[maxStubNum+1] = 338 {true, true, true, false, false, true, true, false, false, true, true}; 339 assert(validStubNum[stubNum]); 340#endif 341 const char *result; 342 if (RetTy->isFloatTy()) { 343 result = sfMips16Helper[stubNum]; 344 } 345 else if (RetTy ->isDoubleTy()) { 346 result = dfMips16Helper[stubNum]; 347 } 348 else if (RetTy->isStructTy()) { 349 // check if it's complex 350 if (RetTy->getNumContainedTypes() == 2) { 351 if ((RetTy->getContainedType(0)->isFloatTy()) && 352 (RetTy->getContainedType(1)->isFloatTy())) { 353 result = scMips16Helper[stubNum]; 354 } 355 else if ((RetTy->getContainedType(0)->isDoubleTy()) && 356 (RetTy->getContainedType(1)->isDoubleTy())) { 357 result = dcMips16Helper[stubNum]; 358 } 359 else { 360 llvm_unreachable("Uncovered condition"); 361 } 362 } 363 else { 364 llvm_unreachable("Uncovered condition"); 365 } 366 } 367 else { 368 if (stubNum == 0) { 369 needHelper = false; 370 return ""; 371 } 372 result = vMips16Helper[stubNum]; 373 } 374 needHelper = true; 375 return result; 376} 377 378void Mips16TargetLowering:: 379getOpndList(SmallVectorImpl<SDValue> &Ops, 380 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 381 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 382 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 383 SelectionDAG &DAG = CLI.DAG; 384 const char* Mips16HelperFunction = 0; 385 bool NeedMips16Helper = false; 386 387 if (getTargetMachine().Options.UseSoftFloat && 388 Subtarget->inMips16HardFloat()) { 389 // 390 // currently we don't have symbols tagged with the mips16 or mips32 391 // qualifier so we will assume that we don't know what kind it is. 392 // and generate the helper 393 // 394 bool LookupHelper = true; 395 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) { 396 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() }; 397 398 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 399 Find)) 400 LookupHelper = false; 401 } else if (GlobalAddressSDNode *G = 402 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 403 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, 404 G->getGlobal()->getName().data() }; 405 406 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 407 Find)) 408 LookupHelper = false; 409 } 410 if (LookupHelper) Mips16HelperFunction = 411 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper); 412 413 } 414 415 SDValue JumpTarget = Callee; 416 417 // T9 should contain the address of the callee function if 418 // -reloction-model=pic or it is an indirect call. 419 if (IsPICCall || !GlobalOrExternal) { 420 unsigned V0Reg = Mips::V0; 421 if (NeedMips16Helper) { 422 RegsToPass.push_front(std::make_pair(V0Reg, Callee)); 423 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy()); 424 JumpTarget = getAddrGlobal(JumpTarget, DAG, MipsII::MO_GOT); 425 } else 426 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee)); 427 } 428 429 Ops.push_back(JumpTarget); 430 431 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 432 InternalLinkage, CLI, Callee, Chain); 433} 434 435MachineBasicBlock *Mips16TargetLowering:: 436emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { 437 if (DontExpandCondPseudos16) 438 return BB; 439 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 440 DebugLoc DL = MI->getDebugLoc(); 441 // To "insert" a SELECT_CC instruction, we actually have to insert the 442 // diamond control-flow pattern. The incoming instruction knows the 443 // destination vreg to set, the condition code register to branch on, the 444 // true/false values to select between, and a branch opcode to use. 445 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 446 MachineFunction::iterator It = BB; 447 ++It; 448 449 // thisMBB: 450 // ... 451 // TrueVal = ... 452 // setcc r1, r2, r3 453 // bNE r1, r0, copy1MBB 454 // fallthrough --> copy0MBB 455 MachineBasicBlock *thisMBB = BB; 456 MachineFunction *F = BB->getParent(); 457 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 458 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 459 F->insert(It, copy0MBB); 460 F->insert(It, sinkMBB); 461 462 // Transfer the remainder of BB and its successor edges to sinkMBB. 463 sinkMBB->splice(sinkMBB->begin(), BB, 464 llvm::next(MachineBasicBlock::iterator(MI)), 465 BB->end()); 466 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 467 468 // Next, add the true and fallthrough blocks as its successors. 469 BB->addSuccessor(copy0MBB); 470 BB->addSuccessor(sinkMBB); 471 472 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) 473 .addMBB(sinkMBB); 474 475 // copy0MBB: 476 // %FalseValue = ... 477 // # fallthrough to sinkMBB 478 BB = copy0MBB; 479 480 // Update machine-CFG edges 481 BB->addSuccessor(sinkMBB); 482 483 // sinkMBB: 484 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 485 // ... 486 BB = sinkMBB; 487 488 BuildMI(*BB, BB->begin(), DL, 489 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 490 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 491 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 492 493 MI->eraseFromParent(); // The pseudo instruction is gone now. 494 return BB; 495} 496 497MachineBasicBlock *Mips16TargetLowering::emitSelT16 498 (unsigned Opc1, unsigned Opc2, 499 MachineInstr *MI, MachineBasicBlock *BB) const { 500 if (DontExpandCondPseudos16) 501 return BB; 502 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 503 DebugLoc DL = MI->getDebugLoc(); 504 // To "insert" a SELECT_CC instruction, we actually have to insert the 505 // diamond control-flow pattern. The incoming instruction knows the 506 // destination vreg to set, the condition code register to branch on, the 507 // true/false values to select between, and a branch opcode to use. 508 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 509 MachineFunction::iterator It = BB; 510 ++It; 511 512 // thisMBB: 513 // ... 514 // TrueVal = ... 515 // setcc r1, r2, r3 516 // bNE r1, r0, copy1MBB 517 // fallthrough --> copy0MBB 518 MachineBasicBlock *thisMBB = BB; 519 MachineFunction *F = BB->getParent(); 520 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 521 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 522 F->insert(It, copy0MBB); 523 F->insert(It, sinkMBB); 524 525 // Transfer the remainder of BB and its successor edges to sinkMBB. 526 sinkMBB->splice(sinkMBB->begin(), BB, 527 llvm::next(MachineBasicBlock::iterator(MI)), 528 BB->end()); 529 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 530 531 // Next, add the true and fallthrough blocks as its successors. 532 BB->addSuccessor(copy0MBB); 533 BB->addSuccessor(sinkMBB); 534 535 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 536 .addReg(MI->getOperand(4).getReg()); 537 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 538 539 // copy0MBB: 540 // %FalseValue = ... 541 // # fallthrough to sinkMBB 542 BB = copy0MBB; 543 544 // Update machine-CFG edges 545 BB->addSuccessor(sinkMBB); 546 547 // sinkMBB: 548 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 549 // ... 550 BB = sinkMBB; 551 552 BuildMI(*BB, BB->begin(), DL, 553 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 554 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 555 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 556 557 MI->eraseFromParent(); // The pseudo instruction is gone now. 558 return BB; 559 560} 561 562MachineBasicBlock *Mips16TargetLowering::emitSeliT16 563 (unsigned Opc1, unsigned Opc2, 564 MachineInstr *MI, MachineBasicBlock *BB) const { 565 if (DontExpandCondPseudos16) 566 return BB; 567 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 568 DebugLoc DL = MI->getDebugLoc(); 569 // To "insert" a SELECT_CC instruction, we actually have to insert the 570 // diamond control-flow pattern. The incoming instruction knows the 571 // destination vreg to set, the condition code register to branch on, the 572 // true/false values to select between, and a branch opcode to use. 573 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 574 MachineFunction::iterator It = BB; 575 ++It; 576 577 // thisMBB: 578 // ... 579 // TrueVal = ... 580 // setcc r1, r2, r3 581 // bNE r1, r0, copy1MBB 582 // fallthrough --> copy0MBB 583 MachineBasicBlock *thisMBB = BB; 584 MachineFunction *F = BB->getParent(); 585 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 586 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 587 F->insert(It, copy0MBB); 588 F->insert(It, sinkMBB); 589 590 // Transfer the remainder of BB and its successor edges to sinkMBB. 591 sinkMBB->splice(sinkMBB->begin(), BB, 592 llvm::next(MachineBasicBlock::iterator(MI)), 593 BB->end()); 594 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 595 596 // Next, add the true and fallthrough blocks as its successors. 597 BB->addSuccessor(copy0MBB); 598 BB->addSuccessor(sinkMBB); 599 600 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 601 .addImm(MI->getOperand(4).getImm()); 602 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 603 604 // copy0MBB: 605 // %FalseValue = ... 606 // # fallthrough to sinkMBB 607 BB = copy0MBB; 608 609 // Update machine-CFG edges 610 BB->addSuccessor(sinkMBB); 611 612 // sinkMBB: 613 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 614 // ... 615 BB = sinkMBB; 616 617 BuildMI(*BB, BB->begin(), DL, 618 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 619 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 620 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 621 622 MI->eraseFromParent(); // The pseudo instruction is gone now. 623 return BB; 624 625} 626 627MachineBasicBlock 628 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 629 MachineInstr *MI, 630 MachineBasicBlock *BB) const { 631 if (DontExpandCondPseudos16) 632 return BB; 633 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 634 unsigned regX = MI->getOperand(0).getReg(); 635 unsigned regY = MI->getOperand(1).getReg(); 636 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 637 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 638 .addReg(regY); 639 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 640 MI->eraseFromParent(); // The pseudo instruction is gone now. 641 return BB; 642} 643 644MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( 645 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, 646 MachineInstr *MI, MachineBasicBlock *BB) const { 647 if (DontExpandCondPseudos16) 648 return BB; 649 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 650 unsigned regX = MI->getOperand(0).getReg(); 651 int64_t imm = MI->getOperand(1).getImm(); 652 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 653 unsigned CmpOpc; 654 if (isUInt<8>(imm)) 655 CmpOpc = CmpiOpc; 656 else if ((!ImmSigned && isUInt<16>(imm)) || 657 (ImmSigned && isInt<16>(imm))) 658 CmpOpc = CmpiXOpc; 659 else 660 llvm_unreachable("immediate field not usable"); 661 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 662 .addImm(imm); 663 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 664 MI->eraseFromParent(); // The pseudo instruction is gone now. 665 return BB; 666} 667 668static unsigned Mips16WhichOp8uOr16simm 669 (unsigned shortOp, unsigned longOp, int64_t Imm) { 670 if (isUInt<8>(Imm)) 671 return shortOp; 672 else if (isInt<16>(Imm)) 673 return longOp; 674 else 675 llvm_unreachable("immediate field not usable"); 676} 677 678MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( 679 unsigned SltOpc, 680 MachineInstr *MI, MachineBasicBlock *BB) const { 681 if (DontExpandCondPseudos16) 682 return BB; 683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 684 unsigned CC = MI->getOperand(0).getReg(); 685 unsigned regX = MI->getOperand(1).getReg(); 686 unsigned regY = MI->getOperand(2).getReg(); 687 BuildMI(*BB, MI, MI->getDebugLoc(), 688 TII->get(SltOpc)).addReg(regX).addReg(regY); 689 BuildMI(*BB, MI, MI->getDebugLoc(), 690 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 691 MI->eraseFromParent(); // The pseudo instruction is gone now. 692 return BB; 693} 694 695MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins( 696 unsigned SltiOpc, unsigned SltiXOpc, 697 MachineInstr *MI, MachineBasicBlock *BB )const { 698 if (DontExpandCondPseudos16) 699 return BB; 700 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 701 unsigned CC = MI->getOperand(0).getReg(); 702 unsigned regX = MI->getOperand(1).getReg(); 703 int64_t Imm = MI->getOperand(2).getImm(); 704 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 705 BuildMI(*BB, MI, MI->getDebugLoc(), 706 TII->get(SltOpc)).addReg(regX).addImm(Imm); 707 BuildMI(*BB, MI, MI->getDebugLoc(), 708 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 709 MI->eraseFromParent(); // The pseudo instruction is gone now. 710 return BB; 711 712} 713