Mips16ISelLowering.cpp revision b359bda93d410623bbbc96dc9968d94447169a79
1//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Subclass of MipsTargetLowering specialized for mips16. 11// 12//===----------------------------------------------------------------------===// 13#define DEBUG_TYPE "mips-lower" 14#include "Mips16ISelLowering.h" 15#include "MipsRegisterInfo.h" 16#include "MipsTargetMachine.h" 17#include "MCTargetDesc/MipsBaseInfo.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Target/TargetInstrInfo.h" 21 22using namespace llvm; 23 24static cl::opt<bool> DontExpandCondPseudos16( 25 "mips16-dont-expand-cond-pseudo", 26 cl::init(false), 27 cl::desc("Dont expand conditional move related " 28 "pseudos for Mips 16"), 29 cl::Hidden); 30 31namespace { 32struct Mips16Libcall { 33 RTLIB::Libcall Libcall; 34 const char *Name; 35 36 bool operator<(const Mips16Libcall &RHS) const { 37 return std::strcmp(Name, RHS.Name) < 0; 38 } 39}; 40 41struct Mips16IntrinsicHelperType{ 42 const char* Name; 43 const char* Helper; 44 45 bool operator<(const Mips16IntrinsicHelperType &RHS) const { 46 return std::strcmp(Name, RHS.Name) < 0; 47 } 48 bool operator==(const Mips16IntrinsicHelperType &RHS) const { 49 return std::strcmp(Name, RHS.Name) == 0; 50 } 51}; 52} 53 54// Libcalls for which no helper is generated. Sorted by name for binary search. 55static const Mips16Libcall HardFloatLibCalls[] = { 56 { RTLIB::ADD_F64, "__mips16_adddf3" }, 57 { RTLIB::ADD_F32, "__mips16_addsf3" }, 58 { RTLIB::DIV_F64, "__mips16_divdf3" }, 59 { RTLIB::DIV_F32, "__mips16_divsf3" }, 60 { RTLIB::OEQ_F64, "__mips16_eqdf2" }, 61 { RTLIB::OEQ_F32, "__mips16_eqsf2" }, 62 { RTLIB::FPEXT_F32_F64, "__mips16_extendsfdf2" }, 63 { RTLIB::FPTOSINT_F64_I32, "__mips16_fix_truncdfsi" }, 64 { RTLIB::FPTOSINT_F32_I32, "__mips16_fix_truncsfsi" }, 65 { RTLIB::SINTTOFP_I32_F64, "__mips16_floatsidf" }, 66 { RTLIB::SINTTOFP_I32_F32, "__mips16_floatsisf" }, 67 { RTLIB::UINTTOFP_I32_F64, "__mips16_floatunsidf" }, 68 { RTLIB::UINTTOFP_I32_F32, "__mips16_floatunsisf" }, 69 { RTLIB::OGE_F64, "__mips16_gedf2" }, 70 { RTLIB::OGE_F32, "__mips16_gesf2" }, 71 { RTLIB::OGT_F64, "__mips16_gtdf2" }, 72 { RTLIB::OGT_F32, "__mips16_gtsf2" }, 73 { RTLIB::OLE_F64, "__mips16_ledf2" }, 74 { RTLIB::OLE_F32, "__mips16_lesf2" }, 75 { RTLIB::OLT_F64, "__mips16_ltdf2" }, 76 { RTLIB::OLT_F32, "__mips16_ltsf2" }, 77 { RTLIB::MUL_F64, "__mips16_muldf3" }, 78 { RTLIB::MUL_F32, "__mips16_mulsf3" }, 79 { RTLIB::UNE_F64, "__mips16_nedf2" }, 80 { RTLIB::UNE_F32, "__mips16_nesf2" }, 81 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_dc" }, // No associated libcall. 82 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_df" }, // No associated libcall. 83 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sc" }, // No associated libcall. 84 { RTLIB::UNKNOWN_LIBCALL, "__mips16_ret_sf" }, // No associated libcall. 85 { RTLIB::SUB_F64, "__mips16_subdf3" }, 86 { RTLIB::SUB_F32, "__mips16_subsf3" }, 87 { RTLIB::FPROUND_F64_F32, "__mips16_truncdfsf2" }, 88 { RTLIB::UO_F64, "__mips16_unorddf2" }, 89 { RTLIB::UO_F32, "__mips16_unordsf2" } 90}; 91 92static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = { 93 {"__fixunsdfsi", "__mips16_call_stub_2" }, 94 {"ceil", "__mips16_call_stub_df_2"}, 95 {"ceilf", "__mips16_call_stub_sf_1"}, 96 {"copysign", "__mips16_call_stub_df_10"}, 97 {"copysignf", "__mips16_call_stub_sf_5"}, 98 {"cos", "__mips16_call_stub_df_2"}, 99 {"cosf", "__mips16_call_stub_sf_1"}, 100 {"exp2", "__mips16_call_stub_df_2"}, 101 {"exp2f", "__mips16_call_stub_sf_1"}, 102 {"floor", "__mips16_call_stub_df_2"}, 103 {"floorf", "__mips16_call_stub_sf_1"}, 104 {"log2", "__mips16_call_stub_df_2"}, 105 {"log2f", "__mips16_call_stub_sf_1"}, 106 {"nearbyint", "__mips16_call_stub_df_2"}, 107 {"nearbyintf", "__mips16_call_stub_sf_1"}, 108 {"rint", "__mips16_call_stub_df_2"}, 109 {"rintf", "__mips16_call_stub_sf_1"}, 110 {"sin", "__mips16_call_stub_df_2"}, 111 {"sinf", "__mips16_call_stub_sf_1"}, 112 {"sqrt", "__mips16_call_stub_df_2"}, 113 {"sqrtf", "__mips16_call_stub_sf_1"}, 114 {"trunc", "__mips16_call_stub_df_2"}, 115 {"truncf", "__mips16_call_stub_sf_1"}, 116}; 117 118Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) 119 : MipsTargetLowering(TM) { 120 // 121 // set up as if mips32 and then revert so we can test the mechanism 122 // for switching 123 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 124 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 125 computeRegisterProperties(); 126 clearRegisterClasses(); 127 128 // Set up the register classes 129 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 130 131 if (Subtarget->inMips16HardFloat()) 132 setMips16HardFloatLibCalls(); 133 134 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 135 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 136 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 137 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 138 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 139 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 140 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 141 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 142 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 143 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 144 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 145 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 146 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 147 148 setOperationAction(ISD::ROTR, MVT::i32, Expand); 149 setOperationAction(ISD::ROTR, MVT::i64, Expand); 150 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 151 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 152 153 computeRegisterProperties(); 154} 155 156const MipsTargetLowering * 157llvm::createMips16TargetLowering(MipsTargetMachine &TM) { 158 return new Mips16TargetLowering(TM); 159} 160 161bool 162Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 163 return false; 164} 165 166MachineBasicBlock * 167Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 168 MachineBasicBlock *BB) const { 169 switch (MI->getOpcode()) { 170 default: 171 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 172 case Mips::SelBeqZ: 173 return emitSel16(Mips::BeqzRxImm16, MI, BB); 174 case Mips::SelBneZ: 175 return emitSel16(Mips::BnezRxImm16, MI, BB); 176 case Mips::SelTBteqZCmpi: 177 return emitSeliT16(Mips::BteqzX16, Mips::CmpiRxImmX16, MI, BB); 178 case Mips::SelTBteqZSlti: 179 return emitSeliT16(Mips::BteqzX16, Mips::SltiRxImmX16, MI, BB); 180 case Mips::SelTBteqZSltiu: 181 return emitSeliT16(Mips::BteqzX16, Mips::SltiuRxImmX16, MI, BB); 182 case Mips::SelTBtneZCmpi: 183 return emitSeliT16(Mips::BtnezX16, Mips::CmpiRxImmX16, MI, BB); 184 case Mips::SelTBtneZSlti: 185 return emitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB); 186 case Mips::SelTBtneZSltiu: 187 return emitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB); 188 case Mips::SelTBteqZCmp: 189 return emitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 190 case Mips::SelTBteqZSlt: 191 return emitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 192 case Mips::SelTBteqZSltu: 193 return emitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 194 case Mips::SelTBtneZCmp: 195 return emitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 196 case Mips::SelTBtneZSlt: 197 return emitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 198 case Mips::SelTBtneZSltu: 199 return emitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 200 case Mips::BteqzT8CmpX16: 201 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB); 202 case Mips::BteqzT8SltX16: 203 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltRxRy16, MI, BB); 204 case Mips::BteqzT8SltuX16: 205 // TBD: figure out a way to get this or remove the instruction 206 // altogether. 207 return emitFEXT_T8I816_ins(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB); 208 case Mips::BtnezT8CmpX16: 209 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB); 210 case Mips::BtnezT8SltX16: 211 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltRxRy16, MI, BB); 212 case Mips::BtnezT8SltuX16: 213 // TBD: figure out a way to get this or remove the instruction 214 // altogether. 215 return emitFEXT_T8I816_ins(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB); 216 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins( 217 Mips::BteqzX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 218 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins( 219 Mips::BteqzX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 220 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins( 221 Mips::BteqzX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 222 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins( 223 Mips::BtnezX16, Mips::CmpiRxImm16, Mips::CmpiRxImmX16, false, MI, BB); 224 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins( 225 Mips::BtnezX16, Mips::SltiRxImm16, Mips::SltiRxImmX16, true, MI, BB); 226 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins( 227 Mips::BtnezX16, Mips::SltiuRxImm16, Mips::SltiuRxImmX16, false, MI, BB); 228 break; 229 case Mips::SltCCRxRy16: 230 return emitFEXT_CCRX16_ins(Mips::SltRxRy16, MI, BB); 231 break; 232 case Mips::SltiCCRxImmX16: 233 return emitFEXT_CCRXI16_ins 234 (Mips::SltiRxImm16, Mips::SltiRxImmX16, MI, BB); 235 case Mips::SltiuCCRxImmX16: 236 return emitFEXT_CCRXI16_ins 237 (Mips::SltiuRxImm16, Mips::SltiuRxImmX16, MI, BB); 238 case Mips::SltuCCRxRy16: 239 return emitFEXT_CCRX16_ins 240 (Mips::SltuRxRy16, MI, BB); 241 } 242} 243 244bool Mips16TargetLowering:: 245isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 246 unsigned NextStackOffset, 247 const MipsFunctionInfo& FI) const { 248 // No tail call optimization for mips16. 249 return false; 250} 251 252void Mips16TargetLowering::setMips16HardFloatLibCalls() { 253 for (unsigned I = 0; I != array_lengthof(HardFloatLibCalls); ++I) { 254 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) && 255 "Array not sorted!"); 256 if (HardFloatLibCalls[I].Libcall != RTLIB::UNKNOWN_LIBCALL) 257 setLibcallName(HardFloatLibCalls[I].Libcall, HardFloatLibCalls[I].Name); 258 } 259 260 setLibcallName(RTLIB::O_F64, "__mips16_unorddf2"); 261 setLibcallName(RTLIB::O_F32, "__mips16_unordsf2"); 262} 263 264// 265// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much 266// cleaner way to do all of this but it will have to wait until the traditional 267// gcc mechanism is completed. 268// 269// For Pic, in order for Mips16 code to call Mips32 code which according the abi 270// have either arguments or returned values placed in floating point registers, 271// we use a set of helper functions. (This includes functions which return type 272// complex which on Mips are returned in a pair of floating point registers). 273// 274// This is an encoding that we inherited from gcc. 275// In Mips traditional O32, N32 ABI, floating point numbers are passed in 276// floating point argument registers 1,2 only when the first and optionally 277// the second arguments are float (sf) or double (df). 278// For Mips16 we are only concerned with the situations where floating point 279// arguments are being passed in floating point registers by the ABI, because 280// Mips16 mode code cannot execute floating point instructions to load those 281// values and hence helper functions are needed. 282// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df) 283// the helper function suffixs for these are: 284// 0, 1, 5, 9, 2, 6, 10 285// this suffix can then be calculated as follows: 286// for a given argument Arg: 287// Arg1x, Arg2x = 1 : Arg is sf 288// 2 : Arg is df 289// 0: Arg is neither sf or df 290// So this stub is the string for number Arg1x + Arg2x*4. 291// However not all numbers between 0 and 10 are possible, we check anyway and 292// assert if the impossible exists. 293// 294 295unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber 296 (ArgListTy &Args) const { 297 unsigned int resultNum = 0; 298 if (Args.size() >= 1) { 299 Type *t = Args[0].Ty; 300 if (t->isFloatTy()) { 301 resultNum = 1; 302 } 303 else if (t->isDoubleTy()) { 304 resultNum = 2; 305 } 306 } 307 if (resultNum) { 308 if (Args.size() >=2) { 309 Type *t = Args[1].Ty; 310 if (t->isFloatTy()) { 311 resultNum += 4; 312 } 313 else if (t->isDoubleTy()) { 314 resultNum += 8; 315 } 316 } 317 } 318 return resultNum; 319} 320 321// 322// prefixs are attached to stub numbers depending on the return type . 323// return type: float sf_ 324// double df_ 325// single complex sc_ 326// double complext dc_ 327// others NO PREFIX 328// 329// 330// The full name of a helper function is__mips16_call_stub + 331// return type dependent prefix + stub number 332// 333// 334// This is something that probably should be in a different source file and 335// perhaps done differently but my main purpose is to not waste runtime 336// on something that we can enumerate in the source. Another possibility is 337// to have a python script to generate these mapping tables. This will do 338// for now. There are a whole series of helper function mapping arrays, one 339// for each return type class as outlined above. There there are 11 possible 340// entries. Ones with 0 are ones which should never be selected 341// 342// All the arrays are similar except for ones which return neither 343// sf, df, sc, dc, in which only care about ones which have sf or df as a 344// first parameter. 345// 346#define P_ "__mips16_call_stub_" 347#define MAX_STUB_NUMBER 10 348#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10" 349#define T P "0" , T1 350#define P P_ 351static char const * vMips16Helper[MAX_STUB_NUMBER+1] = 352 {0, T1 }; 353#undef P 354#define P P_ "sf_" 355static char const * sfMips16Helper[MAX_STUB_NUMBER+1] = 356 { T }; 357#undef P 358#define P P_ "df_" 359static char const * dfMips16Helper[MAX_STUB_NUMBER+1] = 360 { T }; 361#undef P 362#define P P_ "sc_" 363static char const * scMips16Helper[MAX_STUB_NUMBER+1] = 364 { T }; 365#undef P 366#define P P_ "dc_" 367static char const * dcMips16Helper[MAX_STUB_NUMBER+1] = 368 { T }; 369#undef P 370#undef P_ 371 372 373const char* Mips16TargetLowering:: 374 getMips16HelperFunction 375 (Type* RetTy, ArgListTy &Args, bool &needHelper) const { 376 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args); 377#ifndef NDEBUG 378 const unsigned int maxStubNum = 10; 379 assert(stubNum <= maxStubNum); 380 const bool validStubNum[maxStubNum+1] = 381 {true, true, true, false, false, true, true, false, false, true, true}; 382 assert(validStubNum[stubNum]); 383#endif 384 const char *result; 385 if (RetTy->isFloatTy()) { 386 result = sfMips16Helper[stubNum]; 387 } 388 else if (RetTy ->isDoubleTy()) { 389 result = dfMips16Helper[stubNum]; 390 } 391 else if (RetTy->isStructTy()) { 392 // check if it's complex 393 if (RetTy->getNumContainedTypes() == 2) { 394 if ((RetTy->getContainedType(0)->isFloatTy()) && 395 (RetTy->getContainedType(1)->isFloatTy())) { 396 result = scMips16Helper[stubNum]; 397 } 398 else if ((RetTy->getContainedType(0)->isDoubleTy()) && 399 (RetTy->getContainedType(1)->isDoubleTy())) { 400 result = dcMips16Helper[stubNum]; 401 } 402 else { 403 llvm_unreachable("Uncovered condition"); 404 } 405 } 406 else { 407 llvm_unreachable("Uncovered condition"); 408 } 409 } 410 else { 411 if (stubNum == 0) { 412 needHelper = false; 413 return ""; 414 } 415 result = vMips16Helper[stubNum]; 416 } 417 needHelper = true; 418 return result; 419} 420 421void Mips16TargetLowering:: 422getOpndList(SmallVectorImpl<SDValue> &Ops, 423 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 424 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 425 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 426 SelectionDAG &DAG = CLI.DAG; 427 MachineFunction &MF = DAG.getMachineFunction(); 428 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 429 const char* Mips16HelperFunction = 0; 430 bool NeedMips16Helper = false; 431 432 if (getTargetMachine().Options.UseSoftFloat && 433 Subtarget->inMips16HardFloat()) { 434 // 435 // currently we don't have symbols tagged with the mips16 or mips32 436 // qualifier so we will assume that we don't know what kind it is. 437 // and generate the helper 438 // 439 bool LookupHelper = true; 440 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) { 441 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, S->getSymbol() }; 442 443 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 444 Find)) 445 LookupHelper = false; 446 else { 447 Mips16IntrinsicHelperType IntrinsicFind = {S->getSymbol(), ""}; 448 // one more look at list of intrinsics 449 if (std::binary_search(Mips16IntrinsicHelper, 450 array_endof(Mips16IntrinsicHelper), 451 IntrinsicFind)) { 452 const Mips16IntrinsicHelperType *h =(std::find(Mips16IntrinsicHelper, 453 array_endof(Mips16IntrinsicHelper), 454 IntrinsicFind)); 455 Mips16HelperFunction = h->Helper; 456 NeedMips16Helper = true; 457 LookupHelper = false; 458 } 459 460 } 461 } else if (GlobalAddressSDNode *G = 462 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 463 Mips16Libcall Find = { RTLIB::UNKNOWN_LIBCALL, 464 G->getGlobal()->getName().data() }; 465 466 if (std::binary_search(HardFloatLibCalls, array_endof(HardFloatLibCalls), 467 Find)) 468 LookupHelper = false; 469 } 470 if (LookupHelper) Mips16HelperFunction = 471 getMips16HelperFunction(CLI.RetTy, CLI.Args, NeedMips16Helper); 472 473 } 474 475 SDValue JumpTarget = Callee; 476 477 // T9 should contain the address of the callee function if 478 // -reloction-model=pic or it is an indirect call. 479 if (IsPICCall || !GlobalOrExternal) { 480 unsigned V0Reg = Mips::V0; 481 if (NeedMips16Helper) { 482 RegsToPass.push_front(std::make_pair(V0Reg, Callee)); 483 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction, getPointerTy()); 484 ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget); 485 JumpTarget = getAddrGlobal(S, JumpTarget.getValueType(), DAG, 486 MipsII::MO_GOT, Chain, 487 FuncInfo->callPtrInfo(S->getSymbol())); 488 } else 489 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee)); 490 } 491 492 Ops.push_back(JumpTarget); 493 494 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 495 InternalLinkage, CLI, Callee, Chain); 496} 497 498MachineBasicBlock *Mips16TargetLowering:: 499emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { 500 if (DontExpandCondPseudos16) 501 return BB; 502 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 503 DebugLoc DL = MI->getDebugLoc(); 504 // To "insert" a SELECT_CC instruction, we actually have to insert the 505 // diamond control-flow pattern. The incoming instruction knows the 506 // destination vreg to set, the condition code register to branch on, the 507 // true/false values to select between, and a branch opcode to use. 508 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 509 MachineFunction::iterator It = BB; 510 ++It; 511 512 // thisMBB: 513 // ... 514 // TrueVal = ... 515 // setcc r1, r2, r3 516 // bNE r1, r0, copy1MBB 517 // fallthrough --> copy0MBB 518 MachineBasicBlock *thisMBB = BB; 519 MachineFunction *F = BB->getParent(); 520 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 521 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 522 F->insert(It, copy0MBB); 523 F->insert(It, sinkMBB); 524 525 // Transfer the remainder of BB and its successor edges to sinkMBB. 526 sinkMBB->splice(sinkMBB->begin(), BB, 527 llvm::next(MachineBasicBlock::iterator(MI)), 528 BB->end()); 529 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 530 531 // Next, add the true and fallthrough blocks as its successors. 532 BB->addSuccessor(copy0MBB); 533 BB->addSuccessor(sinkMBB); 534 535 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) 536 .addMBB(sinkMBB); 537 538 // copy0MBB: 539 // %FalseValue = ... 540 // # fallthrough to sinkMBB 541 BB = copy0MBB; 542 543 // Update machine-CFG edges 544 BB->addSuccessor(sinkMBB); 545 546 // sinkMBB: 547 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 548 // ... 549 BB = sinkMBB; 550 551 BuildMI(*BB, BB->begin(), DL, 552 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 553 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 554 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 555 556 MI->eraseFromParent(); // The pseudo instruction is gone now. 557 return BB; 558} 559 560MachineBasicBlock *Mips16TargetLowering::emitSelT16 561 (unsigned Opc1, unsigned Opc2, 562 MachineInstr *MI, MachineBasicBlock *BB) const { 563 if (DontExpandCondPseudos16) 564 return BB; 565 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 566 DebugLoc DL = MI->getDebugLoc(); 567 // To "insert" a SELECT_CC instruction, we actually have to insert the 568 // diamond control-flow pattern. The incoming instruction knows the 569 // destination vreg to set, the condition code register to branch on, the 570 // true/false values to select between, and a branch opcode to use. 571 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 572 MachineFunction::iterator It = BB; 573 ++It; 574 575 // thisMBB: 576 // ... 577 // TrueVal = ... 578 // setcc r1, r2, r3 579 // bNE r1, r0, copy1MBB 580 // fallthrough --> copy0MBB 581 MachineBasicBlock *thisMBB = BB; 582 MachineFunction *F = BB->getParent(); 583 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 584 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 585 F->insert(It, copy0MBB); 586 F->insert(It, sinkMBB); 587 588 // Transfer the remainder of BB and its successor edges to sinkMBB. 589 sinkMBB->splice(sinkMBB->begin(), BB, 590 llvm::next(MachineBasicBlock::iterator(MI)), 591 BB->end()); 592 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 593 594 // Next, add the true and fallthrough blocks as its successors. 595 BB->addSuccessor(copy0MBB); 596 BB->addSuccessor(sinkMBB); 597 598 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 599 .addReg(MI->getOperand(4).getReg()); 600 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 601 602 // copy0MBB: 603 // %FalseValue = ... 604 // # fallthrough to sinkMBB 605 BB = copy0MBB; 606 607 // Update machine-CFG edges 608 BB->addSuccessor(sinkMBB); 609 610 // sinkMBB: 611 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 612 // ... 613 BB = sinkMBB; 614 615 BuildMI(*BB, BB->begin(), DL, 616 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 617 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 618 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 619 620 MI->eraseFromParent(); // The pseudo instruction is gone now. 621 return BB; 622 623} 624 625MachineBasicBlock *Mips16TargetLowering::emitSeliT16 626 (unsigned Opc1, unsigned Opc2, 627 MachineInstr *MI, MachineBasicBlock *BB) const { 628 if (DontExpandCondPseudos16) 629 return BB; 630 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 631 DebugLoc DL = MI->getDebugLoc(); 632 // To "insert" a SELECT_CC instruction, we actually have to insert the 633 // diamond control-flow pattern. The incoming instruction knows the 634 // destination vreg to set, the condition code register to branch on, the 635 // true/false values to select between, and a branch opcode to use. 636 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 637 MachineFunction::iterator It = BB; 638 ++It; 639 640 // thisMBB: 641 // ... 642 // TrueVal = ... 643 // setcc r1, r2, r3 644 // bNE r1, r0, copy1MBB 645 // fallthrough --> copy0MBB 646 MachineBasicBlock *thisMBB = BB; 647 MachineFunction *F = BB->getParent(); 648 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 649 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 650 F->insert(It, copy0MBB); 651 F->insert(It, sinkMBB); 652 653 // Transfer the remainder of BB and its successor edges to sinkMBB. 654 sinkMBB->splice(sinkMBB->begin(), BB, 655 llvm::next(MachineBasicBlock::iterator(MI)), 656 BB->end()); 657 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 658 659 // Next, add the true and fallthrough blocks as its successors. 660 BB->addSuccessor(copy0MBB); 661 BB->addSuccessor(sinkMBB); 662 663 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) 664 .addImm(MI->getOperand(4).getImm()); 665 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 666 667 // copy0MBB: 668 // %FalseValue = ... 669 // # fallthrough to sinkMBB 670 BB = copy0MBB; 671 672 // Update machine-CFG edges 673 BB->addSuccessor(sinkMBB); 674 675 // sinkMBB: 676 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 677 // ... 678 BB = sinkMBB; 679 680 BuildMI(*BB, BB->begin(), DL, 681 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 682 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) 683 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); 684 685 MI->eraseFromParent(); // The pseudo instruction is gone now. 686 return BB; 687 688} 689 690MachineBasicBlock 691 *Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, 692 MachineInstr *MI, 693 MachineBasicBlock *BB) const { 694 if (DontExpandCondPseudos16) 695 return BB; 696 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 697 unsigned regX = MI->getOperand(0).getReg(); 698 unsigned regY = MI->getOperand(1).getReg(); 699 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 700 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 701 .addReg(regY); 702 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 703 MI->eraseFromParent(); // The pseudo instruction is gone now. 704 return BB; 705} 706 707MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( 708 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned, 709 MachineInstr *MI, MachineBasicBlock *BB) const { 710 if (DontExpandCondPseudos16) 711 return BB; 712 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 713 unsigned regX = MI->getOperand(0).getReg(); 714 int64_t imm = MI->getOperand(1).getImm(); 715 MachineBasicBlock *target = MI->getOperand(2).getMBB(); 716 unsigned CmpOpc; 717 if (isUInt<8>(imm)) 718 CmpOpc = CmpiOpc; 719 else if ((!ImmSigned && isUInt<16>(imm)) || 720 (ImmSigned && isInt<16>(imm))) 721 CmpOpc = CmpiXOpc; 722 else 723 llvm_unreachable("immediate field not usable"); 724 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(CmpOpc)).addReg(regX) 725 .addImm(imm); 726 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target); 727 MI->eraseFromParent(); // The pseudo instruction is gone now. 728 return BB; 729} 730 731static unsigned Mips16WhichOp8uOr16simm 732 (unsigned shortOp, unsigned longOp, int64_t Imm) { 733 if (isUInt<8>(Imm)) 734 return shortOp; 735 else if (isInt<16>(Imm)) 736 return longOp; 737 else 738 llvm_unreachable("immediate field not usable"); 739} 740 741MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( 742 unsigned SltOpc, 743 MachineInstr *MI, MachineBasicBlock *BB) const { 744 if (DontExpandCondPseudos16) 745 return BB; 746 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 747 unsigned CC = MI->getOperand(0).getReg(); 748 unsigned regX = MI->getOperand(1).getReg(); 749 unsigned regY = MI->getOperand(2).getReg(); 750 BuildMI(*BB, MI, MI->getDebugLoc(), 751 TII->get(SltOpc)).addReg(regX).addReg(regY); 752 BuildMI(*BB, MI, MI->getDebugLoc(), 753 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 754 MI->eraseFromParent(); // The pseudo instruction is gone now. 755 return BB; 756} 757 758MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins( 759 unsigned SltiOpc, unsigned SltiXOpc, 760 MachineInstr *MI, MachineBasicBlock *BB )const { 761 if (DontExpandCondPseudos16) 762 return BB; 763 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 764 unsigned CC = MI->getOperand(0).getReg(); 765 unsigned regX = MI->getOperand(1).getReg(); 766 int64_t Imm = MI->getOperand(2).getImm(); 767 unsigned SltOpc = Mips16WhichOp8uOr16simm(SltiOpc, SltiXOpc, Imm); 768 BuildMI(*BB, MI, MI->getDebugLoc(), 769 TII->get(SltOpc)).addReg(regX).addImm(Imm); 770 BuildMI(*BB, MI, MI->getDebugLoc(), 771 TII->get(Mips::MoveR3216), CC).addReg(Mips::T8); 772 MI->eraseFromParent(); // The pseudo instruction is gone now. 773 return BB; 774 775} 776